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One possibility, set a flag in main() when you want to execute the two lines of code, and if
ISR fires and it finds the main() flag set, it sets another flag, saves value in a temp register,
exits. When 2 lines finish then test for flag from ISR, and update variable if set and clear ISR
flag.
Or look at disabling the interrupt, but leaving it pending, and re-enabling after two lines of code
have executed. Take a look at interrupt controller in TRM manual for further info.
Regards, Dana.
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I didn't understand what you want to do clearly.
and what is your ploblem was.
Disabling the global interrupt doesn't work only for you? that is odd
What is atomic operations?
Is that like a kind of test-and-set operation on assembler language?
You would be better write your code here.
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ATOMIC operation in computing
" There isn't any intermediate state that's visible before it completes.
So if your CPU gets interrupted, or if another task(in multitasking system)
is accessing the same memory, it doesn't affect the result, and these
other operations will observe it as either completed or not started."
In your case.
I think what you should do is
1. Ensuring there is no interrupt when you are reading/writing/updating that variable.
2. The function needs to disable interrupt while reading the variable and set a flag to indicate that
it was read. enable interrupt after reading the value.
The ISR would disable interrupts that would access that variable first, then read and clear the flag
and based on the flag, perform the correct operation of the variable.
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Exactly for this purpose there are CyEnterCriticalSection() and CyExitCriticalSection() are for. Have a look into the "System Reference Guide" (Creator 3.0 -> Help -> System Reference).
It does not make the instructions in between atomic, but it temporarily disables all interrupts for an area of code and safely re-enables it.
Additionally consider to declare those variables that are changed from an interrupt handler as "voilatile" which will prevent errors coming from the excessive (but very good) optimization step in GCC.
Bob
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Some more explanation:
You will not "miss" any interrupt when disabling interrupts, you just will delay its handling for some CPU-instructions. The PSoC4-internal Interrupt Controller Unit (ICU) will remember any interrupt occuring during a disabled time. When enabled back again the interrupt will fire after execution of the next instruction. Only when an interrupt is applied twice while disabled there is the chance that the second one is missed.
Bob
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hi bob ,
regarding your post:
Some more explanation:
You will not "miss" any interrupt when disabling interrupts, you just will delay its handling for some CPU-instructions. The PSoC4-internal Interrupt Controller Unit (ICU) will remember any interrupt occuring during a disabled time. When enabled back again the interrupt will fire after execution of the next instruction. Only when an interrupt is applied twice while disabled there is the chance that the second one is missed.
Bob
Is it documented in one of the psoc pdfs? I would like to send it to a client.
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There is a documentation from ARM explaining in depth the exception (ARM terminology for interrupts) handling. Another source is the documentation for the PICU (Peripheral Interrupt Controller Unit) which is responsible for enabling, masking and priority chaining interrupts.
Bob
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Your __ATOMIC... operations are ment to work on threads sharing the same memory. Since threading needs an operating system that really supports threads and your PSoC4 doesn't have got one this are the wrong functions. These just prevent task-switching while the shared memory is accessed.
Bob