What means high-z impedance exactly?

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Anonymous
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Hi, i cant find a note about the impedance of an analog, high z GPIO in the datasheet . Can anyone tell me that? Even in the OPamp datasheet is no info. thanks a lot

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HeLi_263931
Level 8
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High-Z means 'high input impedance'. That in turn means that the inputs don't put a load on the output / circuit they are connected to.

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Anonymous
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Thanks for the answer but i mean a value for the impedance, how many ohms?

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Bob_Marlowe
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Look into the PSoC3 Family Datasheet to be found here: www.cypress.com/.

   

On page 75 (english version) you find IIL given as 2nA maximum @ 3V from which you may calculate the input impedance using Ohm's law.

   

 

   

Bob

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Anonymous
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Okay. Thank you

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ETRO_SSN583
Level 9
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Hi Z is a state of all drivers on pin turned off, such that all that remains

   

is leakage current of the input protection diodes, and the leakage of the

   

N & P mosfets turned off.

   

 

   

Keep in mind this leakage is a strong function of temp, so spec in datasheet

   

is just a limiting value at room temp. If you are driving external MOSFET gates

   

or Bipolar base connections, you need a R to gnd for MOSFET, or R to emitter for

   

Bipolar to absorb worst case leakage to keep external device from turning on when

   

a pin is tri-stated. R is computed from worst case leakage and thereshold for external

   

device.

   

 

   

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ETRO_SSN583
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One correction, in case of MOSFET, R connections Gate to Source

   

for enhancement mode devices.

   

 

   

Regards, Dana.

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Bob_Marlowe
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@Dana regarding leakage current and temperature: Datasheet says

   

   

       

   

 

   

 

   

   

Specifications are valid for –40°C

            T    A        85°C and T    J        100°C
   

   

Bob

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ETRO_SSN583
Level 9
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@Bob, from datasheet, 25 C value (and a note its a characterization spec not a tested

   

spec) -

   

 

   

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Bob_Marlowe
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Oops, I just stuck to the hedline and didn't look for the fine print.

   

 

   

Bob

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DennisS_46
Employee
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Bob, and others:

   

It's a little more subtle than that.

   

The input leakage is a current spec, it can leak to either rail, that's why it's absolute value. The nature of the current is to double every 10 deg C, and it's speced at the limit temperature, TJ= 100 C. Again, it's a current, not a resistance to Vss or Vdd.

   

There is a difference between "high-Z" and "high-Z analog." "High-Z" is a digital input, it has a small amount of hysteresis (~50 mV) on the digital threshold to prevent noise problems. The hysteresis causes a little bit of charge kick-back to the input pin at the transition. "High-Z analog" disables the hysteresis to yield cleaner ANALOG input waveforms in the case of a high source impedance. This is long standing PSoC practice, goes back to the first chips shipped in 2001.

   

---- Dennis Seguine

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ETRO_SSN583
Level 9
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@Seg, I understand the doubling every 10 C, classic diode behaviour, but what

   

about MOSFET leakage which does not follow that behaviour ? Does diode leakage

   

dominate or Igss and Idsoff in the N and P FETs ?

   

 

   

Regards, Dana.

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Anonymous
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 @set. Thanks for information about the effects of the hysterisis of the digital input. 

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