Anonymous
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Dec 04, 2013
06:20 AM
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Dec 04, 2013
06:20 AM
Can i use any Component in my verilog code by instantiating it?
6 Replies
Dec 04, 2013
06:56 AM
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Dec 04, 2013
06:56 AM
I think you can only instantiate component which are defined in Verilog themselves. This should everything defined as 'primitive'.
Anonymous
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Dec 04, 2013
07:19 AM
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Dec 04, 2013
07:19 AM
So, I can instantiate only components with .v file, right?
Dec 04, 2013
09:05 AM
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Dec 04, 2013
09:05 AM
Yes.
Anonymous
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Dec 05, 2013
04:47 AM
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Dec 05, 2013
04:47 AM
Please, help me with this. I'm trying to instantiate "cy_dffe_v1_0" just for a example and i'm getting this error:
"M0120:Can't find 'cy_dffe_v1_0" in library 'work' with path 'lcpsoc3'.
Dec 05, 2013
07:20 AM
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Dec 05, 2013
07:20 AM
the DFFs are defined in rtl.v, as
module cy_dff (d, clk, q);
So maybe you want to include that one? (The definition of cy_dffe_v1_0 is empty, if you look at the file...)
Anonymous
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Dec 05, 2013
10:32 AM
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Dec 05, 2013
10:32 AM
That's true.
Thank you for your help.