Dummy read cycle is used during the transition from read cycle to write cycle to avoid bus contention.
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During read operation the data lines will be driven by the SRAM. But for write cycle the data lines have to be tristated and the lines will be driven externally. If proper timings are met and data is given after the data line goes in to High Z state; the device will operate correctly. But if proper timings are not met bus contention can happen. For operating in a safer side, a dummy read cycle can be introduced in between read and write cycle. During the dummy read data lines will be in high impedance condition and in the next cycle the data to be written can be given.