Memory alignment

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StBa_721356
Level 5
Level 5
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What are the memory alignment restrictions with the BCM20736 and BCM20737?

Is it allowed to do a 16-bit access on a not-16-bit-aligned address?

Is it allowed to do a 32-bit access on a not-32-bit-aligned address?

If not then is there a kind of exception handling for unaligned memory access and what are the performance penalties for this?

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asridharan
Employee
Employee
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The CPU core is an ARM Cortex M3 which supports unaligned accesses (so no exceptions will be thrown). However, there is a performance penalty - the instruction will take multiple cycles to complete and the pipeline will stall (see ARM documentation). Load/Store multiple instructions do not support unaligned accesses.

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asridharan
Employee
Employee
10 comments on KBA 5 comments on KBA First comment on KBA

The CPU core is an ARM Cortex M3 which supports unaligned accesses (so no exceptions will be thrown). However, there is a performance penalty - the instruction will take multiple cycles to complete and the pipeline will stall (see ARM documentation). Load/Store multiple instructions do not support unaligned accesses.