DMA transfer to Control Reg

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Anonymous
Not applicable

Has anyone used successfully DMA transfer to Control Reg? I have tried many times without success.

   

The difficult part seems to be the correct address of the Control Register. What is wrong with the following TD address definition?

   

 

   

        CyDmaTdSetAddress(DMA_1_TD[0], LO16((uint32)ADC_SAR_1_SAR_WRK0_PTR),
                      LO16((uint32)Control_Reg_1_Control_PTR));

   

 

   

DMA transfer to DAC register works fine.

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Bob_Marlowe
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Why are you trying to output the SAR to a control register which is an input device? Wouldn't it be better to use a status register instead?

   

 

   

Bob

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HeLi_263931
Level 8
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Ouf-of-coffee-error? ( http://www.cypress.com/?docID=43174 )

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HeLi_263931
Level 8
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@esa: can you post the complete DMA init code? Maybe the error is somewhere else? Or maybe even upload the complete project (File / Create workspace bundle - but don't use Chrome for upload).

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Bob_Marlowe
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Ooops, getting late...

   

@hli: Will I see you at "Embedded World"?

   

 

   

Bob

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HeLi_263931
Level 8
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@bob - unfortunately no. I'm doing the electronics stuff just as hobby, so going to an event like this is usually no option 😞

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Anonymous
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Thank you for your interest to my problem. I have managed to solve the SAR ADC to Control reg transfer problem partly with help from Cypress, but there seems to be something mystical going on.

   

I'll attach two cases with one working and the other one giving errors during build. The only difference between these two projects is a different name for the project and two 8-bit pins removed from the other. It seems like you can't predict which change to the design is going to end up with build errors.

   

Maybe there is a simple reason for this. Maybe it is an error in PSoC Creator tool.

   

I wonder if any of you has similar experiences.

   

 

   

ps. It seems like I can include only one file with this response. I'll add the other one to my next reply.

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Anonymous
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Here is my other project.

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Bob_Marlowe
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This is an optimization problem. Since the input to the Mux select is a constant "1" the part using the selected input "0" could be optimized-out, so the ControlRegh1 was removed and the APIs are looking into nirwana...

   

The working design has additionally some IO-pins connected which prevent the registers from getting optimized-out.

   

 

   

 

   

Bob

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Anonymous
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Thank you Bob. That makes sense.

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