DMA Channel, DMA Buffers and DMA Flags

[Anonymous]

Hello,

   

Could you explain me some behaviour and dependencies of DMA?

   

    I want to configure 1 DMA channel from P-Port to USB with several buffers.

   

    Is it possible that P-Port socket writes data to one buffer and USB socket reads from another buffer simultaniously?

   

   What minimal number of buffers do I need to configure for this DMA channel  to do this?

   

   How does size of one buffer depend on USB endpoint configuration?

   

   How does number of buffers depend on USB endpoint configuration?

   

   How does DMA ready flag depend on DMA buffers state?

   

   Does it describe only one buffer state or all buffers state?

   

   Does 'active' state indicate buffer readiness to write?

   

   How does DMA watermark flag depend on DMA buffers state ?

   

Best regards,

   

Olga.

[Anonymous]

 Hi,

       

 I want to configure 1 DMA channel from P-Port to USB with several buffers.

   

(A) Yes, this can be done.

       

    Is it possible that P-Port socket writes data to one buffer and USB socket reads from another buffer simultaniously?

   

   What minimal number of buffers do I need to configure for this DMA channel  to do this?

   

(A) Yes, this is possible. You need to have a minimum of two buffers for this. One will be engaged by the P-port and the other will be engaged by the USB block.

       

   How does size of one buffer depend on USB endpoint configuration?

   

   How does number of buffers depend on USB endpoint configuration?

   

(A) It is generally good practice to declare buffer sizes which are a multiple of endpoint max packet size. Number of buffers in the DMA channel does not really have a relation to endpoint config. But it is good practice to have as many buffers as the burst size configured in endpoint config.

       

   How does DMA ready flag depend on DMA buffers state?

   

   Does it describe only one buffer state or all buffers state?

   

   Does 'active' state indicate buffer readiness to write?

   

   How does DMA watermark flag depend on DMA buffers state ?

   

(A) For a channel that outputs data to the P-port (to external chip/device), the DMA ready flag indicates whether or not there is data ready to be read out from any of the buffers. If there is at least one buffer with data committed to the P-port, DMA ready flag is deasserted. It is essentially a empty flag in this case.

   

For a channel that inputs data to the P-port (from external chip/device), the DMA ready flag indicates whether or not there is buffer area available to write into. If there is at least one buffer available to be filled with data, the DMA ready flag is deasserted. It is essentially a full flag in this case.

   

The polarity of this flag can be set in GPIFII Designer.

   

While the DMA ready flag operation depends on how many buffers in the channel are available, the DMA watermark tells you how many bytes in a buffer are available. You can set the watermark level in firmware using a API.

   

The watermark is generally used so that the external processor interfaced to FX3's GPIF gets an early notification of the buffer full event. All flags within FX3 have a min. 2 cycle delay between the actual event and its notification propagating to the GPIF interface. So the watermark flag helps overcome this limitation.

           

Regards

   

Shashank

[Anonymous]

Helllo,

   

Thank you very much for so detailed answer.

   

It was very usefull for me.

   

King Regards,

   

Olga.

[Anonymous]

 Your answer is a little confusing.

   

For a channel that inputs data to the P-port (from external chip/device), the DMA ready flag indicates whether or not there is buffer area available to write into. If there is at least one buffer available to be filled with data, the DMA ready flag is deasserted. It is essentially a full flag in this case.

   

You are using the word "deassert" which to me means the signal is in its false state. i.e. deassert means DMA Ready is not true. If the signal is active-high, then deassert would mean that it is at a logic low level.

   

Is this how you are intending the description? You say that if there is at least one buffer ready the DMA Ready de-asserts? I would have expected that if the GPIF interface is able to receive data into a buffer then DMA Ready would be asserted (i.e. become active, meaning logic high for active-high signals).

   

Can you please clarify?

   

While the DMA ready flag operation depends on how many buffers in the channel are available, the DMA watermark tells you how many bytes in a buffer are available. You can set the watermark level in firmware using a API.

       

Page 17 of AN65974 states that a partial flag cannot be used to signal the availability of a socket, but it does not explain why this is the case.  If I have 4kB DMA buffers and set the partial flag to assert (become active) when the buffer has less than 4096 bytes in it can I not use this flag to indicate that there is a completely empty buffer available?

[Anonymous]

 I wanted to share the information I got from Cypress which clears things up considerably. +1 for their support case workers, thank you!

   

First, "DMA_RDY" is actually a signal that is asserted when there is no DMA buffer available to satisfy the request (read or write) -- this is very confusing because "DMA Ready" to myself and anyone I've asked sounds like a signal that is asserted when the DMA operation should proceed.  Anyway... If you think of the signal as "DMA NOT AVAILABLE" then things start to make a lot of sense. The example given to me helps this understanding:

   

Let's say you have a DMA descriptor with 4 1kB DMA buffers. Let's also say you want the transfer to take data from GPIF and transfer it into the FX3 (i.e. a DMA IN operation). When the system is first initialized, all four buffers are empty. Since there is at least one buffer available, DMA_RDY will NOT be asserted.  The FPGA transfers 1kB of data. Now you have 1 buffer full, 3 buffers empty. DMA_RDY will remain in its inactive state. The FPGA transfers another 1kB... now you have 2 full, 2 empty, and DMA_RDY stays inactive. Transfer another 1kB. 3 full, 1 empty, DMA_RDY still inactive.  Transfer 1kB. Now you have 4 full, 0 empty. DMA_RDY now asserts. Remember that DMA_RDY really means "DMA not ready".

   

The DMA_RDY flag will remain asserted now until one of those buffers is completely emptied (e.g. it was consumed by the USB peripheral). Now you have 3 full, 1 empty and since there is at least one DMA buffer available to transfer, DMA_RDY will de-assert, signalling the FPGA that it can now transfer data again.

   

I have specifically used the words assert/active and de-assert/inactive beause the flag can be configured as active-high or active-low. While remedial, I will include this for completeness: for an active-high signal, assert means that the output will be at a logic high, and de-assert means the output will be at a logic low.  For an active-low signal, the opposite is true. i.e. for active-low, when the signal is asserted, the pin is at a logic low, and when it is de-asserted, the pin is at a logic high.

   

Personally, I was confused by two aspects of this flag:

   

    
1. DMA_RDY means "DMA not ready" or "DMA full" -- it asserts when a DMA transfer cannot be performed
    
2. The DMA_RDY flag reports the availability of ANY buffer in the descriptor for the DMA thread, not the current buffer. This makes a lot of sense in hindsight.
   

   

Regarding the DMA_PARTIAL flag:

   

The DMA PARTIAL flag cannot be used to start a DMA transfer because the state of this flag is indeterminate during the time when the descriptor is being updated to use the next buffer. This is not described in the documentation. This is why DMA_RDY must be used to start a transfer, and DMA_PARTIAL can be used to end a transfer if simple data counting is insufficient.

   

It would be greatly appreciated if the documentation were updated to elaborate on these points. The naming of this flag is really, really bad.

[Anonymous]

Thanks for the info!

       

-10 for the documentation team though.  An example project is required IMHO

       

And why are we not getting this direct from Cypress employees?

[chju_284486]

Hi akohlsmith

   

 I can not understand "DMA_PARTIAL can be used to end a transfer if simple data counting is insufficient", can you explain it in detail?

   

Thanks!

[Anonymous]

Hi,

   

So is there some special steps to take to make sure that these DMA buffer does not interact/overlap with each other. Will it be safe just by setting the dmaConfig.size respectively? For example, setting the one for the channel of USB3.0 data transfer to 16K and then setting another one 16 byte for other DMA channels. Will they just work fine?

[Anonymous]

I failed in trouble with DMA now, the above comments maybe are useful for me. 

   

I should take some time to understand these information.