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In my project PLL drives Master_Clk.
I need to start the program with XTAL as PLL source and then after some setup switch PLL to DSI or Pin signal.
I gues it is possible, because corresponding functions could be find in CyLib.c and PLL.c.
But what is the exact sequence I have to execute correctly to prevent uC hangs up during the procedure?
Thanks in advance,
Vladimir
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These might help -
http://www.cypress.com/?rID=37884 AN54439
http://www.cypress.com/?rID=40990 AN60631
Regards, Dana.
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That may be a case for Cypress support.
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Also look at the clocking section of the Architecture TRM -
http://www.cypress.com/?app=search&searchType=advanced&keyword=&rtID=117&id=4562
Regards, Dana.
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Thanks for answers,
yes, I saw these documents, but there are no API examples and I'm afraid there are some underwater stones.
In the function comments(Cylib.c) there are mentions that PLL must be stopped before source switching. So, I wonder how to drive uC at this moment.
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This ap note shows the chain of actions necessary for controling PLL,
and calls out the registers for manipulation, which would be in register
TRM. Might shed some light on an approach you could try.
http://www.cypress.com/?docID=44199 AN77900
And or file a CASE to and post back to forum what you find out.
To file a tech case -
“Support”
“Technical Support”
“Create a MyCase”
Regards, Dana