Fine tune PWM frequency of 32768 Hz within +/-5Hz range

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Hi,

   

I need to finely tune frequency of PWM output of PSoC 5LP within approx +/-10Hz, centered at 32.768 kHz (standard Quartz oscillator frequency). I need such fine-tuning to syncronize 32.76 kHz signals on two separate devices within approx. <0.5 Hz. (clock sharing between devices is NOT possible). I thought that all Quartz resonators are closely matched, but as I go through them, frequency deviation from one to another can be as much as 10 Hz. I can pre-select a pair of relatively closely matched Quartz resonators, but some fine adjustment of the frequency is still required.

   

Is there any PLL possibilities of PSoC5LP for fine adjustment of the output frequency with resolution 0.1 Hz? What other possibilities exist to fine-tune Quartz frequency: adjusting Quartz oscillator driving voltage, changing bypassing capacitors, temperature?

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6 Replies
ViDv_264506
Level 5
Level 5
50 sign-ins 25 sign-ins 5 solutions authored

Hi odissey1, 

   

try to use temperature compensated quartz oscillator TCXO as frequency source to the PSoC5LP verilog based DDS. With 32bit or more e. g. 48 bit deep DDS accumulator you can easily achive 0.0000x Hz DDS resolution.

   

Regards, 

   

Viktor

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ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

The typical osc circuit is two caps to create proper loading and

   

feedback. Pierce architecture.

   


   

You could consider connecting an additional cap to circuit and its ground

   

side to an open drain output. By controling the switching to the cap the effective

   

reflected Z will change, thereby changing the osc frequency. You would have

   

to experiment with this approach, and it potentially couple s clock noise into

   

the 32 Khz.

   

 

   

Another approach use a varicap controlled by a pwm followed by a LP filter to

   

generate bias, or a VDAC.

   


   

Just a thought, some possibilities.

   

 

   

    

   

          http://www.ti.com/lit/an/szza043/szza043.pdf

   

 

   

Regards, Dana.

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Anonymous
Not applicable

For +/- 0.5hz, you need 15ppm, as you are compare two devices, that means your tolerance is now half, ie 7.5ppm.That means you need to use TCXO, but those TCXO seems to be more at mhZ range than 32khz.

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

 To dvorakvic,

   

thanks, DDS seems what I need. Can you give more info or link to how to DDS can be done on PSoC5LP?

   

odissey1

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ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

The DDS approach achieves resolution via use of very high frequency

   

clock, and adds appreciable cost to the design, complicates board

   

certification for various standards, so some questions are

   

in order -

   

 

   

1) Do you need adaptive synch of clocks over T and V ?

   

2) Do you care about absolute accuracy of the two 32 Khz clocks, or just

   

need relative accuracy ?

   

3) Cost allowed for the solution part of this problem ?

   

 

   

Regards, Dana.

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Anonymous
Not applicable

 DDS should give you the resolution you want. But the output still be affected by the stability of your clock souce. 

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