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Test set up is :
one power module (to generate 5v) generates V1 = 5V.
one PSoC5 (both analog and digital voltages are at V1).
and a input signal to PSoC at the level of (V1) *1/2. This signal comes almost simultaneously with V1.
Test case 1 :
At the begining, power module starts but due to some reason generates V1 = 2.5V and stucked.
Test case 2 :
At the begining, power module starts but due to some reason generates V1 = 1.5V and stucked.
Test case 3 :
At the begining, power module starts but due to some reason generates V1 = 2.5V and after some retry it generates 5V.
In all cases, will PSoC be damaged?
- Labels:
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PSoC 5LP
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As long as the voltage at the pin is between 0V and the VCC, it should be OK. Notice there are VCC to all 4 quardants of the chip.
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You have to sequence Vdda first before Vddd if theyu are not the same.
GPIO are limited in spec sheet -
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Screenshot attached.
Note if you violate these restrictions you can get latchup which can damage a part.
http://en.wikipedia.org/wiki/Latchup
Regards, Dana.
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VCCD wont take long to rump up so if Vsignal is V1*1/2 all the time then you wont have any problem as long as V1*1/2 is lower than VCCIO and VCCIO is lower than VCCA/VCCD
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In datasheet at "DC Specifications" recommended min value of VDDA is 1.8V, that's why I put second test case.
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Use a DSO to establish timing of ramp to see if you are violating
specs.
Note bulk caps like tants and electrolytics have large C tolerances,
influence power ramp timing, and should be trialed at tolerance
extremes to make sure ramp of one supply will not be in violation
of chip specs.
Regards, Dana.
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pratik, if VDDA <1.8v , the PSOC might not work properly or might not work at all but it won't be damaged as long as there is no other higher voltage signal or power rail.