8 Replies Latest reply on May 29, 2014 6:16 AM by dakn_263916

    Problem with discriminated counting

    shba_282106
    shba_282106 May 29, 2014 6:16 AM

      Hi all!

         

      This project is supposed to count all  pulses lying in an amplitude window in two parallel channels C1 and C2 for 10 seconds. Both C1 and C2 are supposed to report counts independently in their programmed window and keep updating  and displaying on PC through a USBUART interface.

         

      One problem that has been persistent is that quite often one of the channels C1 or C2 measures 65535-n counts instead of n counts. It settles in some time but appears randomly. Default amplitude window for channel 1 is 1to 1.5V and for channel 2 is 2 to 2.5V. The data is attached as a text file as well as the project.

         

      Please see

         

      thanks

         

      Neha

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        • 2. Re: Problem with discriminated counting
          JoMe_264151
          JoMe_264151 Apr 9, 2014 4:50 AM (in response to shba_282106)

          Two things come to my mind:

             

          To start all counters at the same time you should use a control register, reset the counters and start them anew. Keep in mind that the reset-pulse is not asynchronous.

             

           

             

          Check the count signals (route them to a pin) for ringing.

             

           

             

           

             

          Bob

          • 3. Re: Problem with discriminated counting
            dakn_263916
            dakn_263916 Apr 9, 2014 5:52 AM (in response to shba_282106)

            You need to sync all counter activity, not just the enable bit but also the VDAC

               

            updates (eg. cntrs should be reset after VDAC update) so that they  are all

               

            looking at the same window in time and V ? Or does that matter ? Also cntrs

               

            should be all read when stopped (if window in time important).

               

             

               

            Additionally you have configed as up cntrs, reloaded (65535) on Tc. Is that what you wanted ?

               

            Seems that period value should be set to 0 in properties, not 65535 as you now have time set.

               

            Seems like reload should not happen on Tc as well. And you don't need reload checked on

               

            capture either.

               

             

               

            Then in the DO loop you init() followed by a write() of 0. The init resets cntr to its properties values,

               

            which is 65535, then you write 0x0000 to cntr. Seems like the init() did not accomplish much.

               

             

               

            Lastly, if counts should exceed 16 bit value then you need to detect rollover in code or use a bigger

               

            cntr.

               

             

               

            Regards, Dana.

            • 4. Re: Problem with discriminated counting
              shba_282106
              shba_282106 May 29, 2014 12:08 AM (in response to shba_282106)

              Thnx Bob,

                 

              is it necessary to use a control register to reset the counters? Is there any other way throgh software?

              • 5. Re: Problem with discriminated counting
                shba_282106
                shba_282106 May 29, 2014 12:52 AM (in response to shba_282106)

                Thnx Dana,

                   

                Amplitude window should be fixed before the signal appears. Datasheet says it may take about 25us for DAC to settle and since counting time will be no less than 10 seconds, I dint put a delay. However if counters have to be reset after each update how do i do it in code? I dint see any Counter reset API :(

                   

                And yes, all counters should look at the same window as i dint sample and hold the analog input. As soon as a delay of 10 seconds is over, all counters should be read and ready themselves for next counting if the signal lies in desired amplitude window.

                   

                Am not very clear how the period value setting will effect. Should it be set to zero? What should Reload counter settings be in this case? Pulses should be up counted from zero to a value it accumulates in 10 seconds such that counts per 10 seconds are reported.

                   

                Am not getting 65535-n problem if i subtract values from two counters only after checking that lesser is subtracted from greator. But that is not very appropriate to do as am not resetting the counter. Some times same values are repeated many times even if input pulses' amplitude is changed. Attaching the modified project

                • 7. Re: Problem with discriminated counting
                  JoMe_264151
                  JoMe_264151 May 29, 2014 3:05 AM (in response to shba_282106)

                  Re: ontrol register to start all counters:

                     

                  It depends on how precise you want to start your counters synchronously. Some asm-instructions give a delay ín the range of a couple of µs, while a digital signal as coming from a control-register only gives a delay in the range of ns. It all depends on the speed of your clock, you may miss one pulse.

                     

                  Resetting a counter is done in software as: Stop counter, write new counter value (zero for up-count 64K for down-count) then counter is considered to be resetted.

                     

                   

                     

                  Bob

                  • 8. Re: Problem with discriminated counting
                    dakn_263916
                    dakn_263916 May 29, 2014 6:16 AM (in response to shba_282106)

                    Your counters, set as up counter, period should be set to 0. You have them configed

                       

                    to reload period when a reset = 0. So generate reset from a control register or a timer

                       

                    fed to both counters.

                       

                     

                       

                    You also have the reload set to Tc event. If you want capability to collect more than

                       

                    65535 pulses, then either use wider counter, or test for rollover and add the additional

                       

                    accounts when rollover detected. Note this would expand count to 2 X 65535. In this case

                       

                    do not enable reload on Tc.

                       

                     

                       

                    Additional sychronicity could be achived by using a sync module at the output of both

                       

                    comparators, synced to bus clock. Of use a 10 sec timer to create a HW window to

                       

                    trigger everything off. If you wanted to synch the VDACs Verilog solution only real

                       

                    effective solution where simultaneous writes could occur to both VDACs from synced

                       

                    registers.

                       

                    VDAC settling time (large signal) is