I think I've managed to resolve the timing issue with the sequencing SAR. It appears that sequencers are required between the ADC_SAR component's "eos" and "eoc" outputs and their respective inputs on the bSAR_SEQ Verilog component.
Here is my updated schematic. It meets timing even with a 64MHz BusClk and an 18MHz sample clock, which are the limits for this part. I meet timing across the 0C-85C temp range, but fall just shy over the full (-40C-85C) range. Reducing the clock to 50Mhz would make it work over the entire temp range.
