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Hi,
I want to create an algorithmic delta sigma ADC as part of a project.
An algorithmic delta sigma ADC is a 1 loop Delta sigma ADC with a S&H unit that enables us
to divide to sampling process to several stages, in each we sample the error of the previous stage.
The error is the analog voltage residue in the integration capacitor after the first stage of A2D conversion, see attached block diagram.
My goal is to implement at least 2 to such ADC's that work in parallal.
As I understand it each ADC require 2 switch capacitors (SC) units, one for the integrator and another for the S/H unit.
Is it possible to implement it with just 1 SC unit?
I'm wondering whether I should use PSOC 1 or PSOC 5.
PSOC 1 has 8 SC blocks but has a maximum clock of 12 MHz.
PSOC 5 has only 4 SC blocks, but has a maximun clock of 80 MHz.
If there isn't a reason to limit the Delta Sigma sampling rate it seems like PSoc 5 is the better choice.
Am I missing anything?
Also, I am un able to find in integrator block, or a switch capacitor block, in PSoC creator 3.0. Any ideas
where I can find one of these?
Thanks
,Peli
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PSoC 5LP
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Could turn out to be a difficult task.
In PSoC1 there is a decimator used together with the ADC and there is only one decimator.
In PSoC5 the ADC uses some fixed-function blocks which cannot be built from other resources.
And afaik there is no PSoC containing two DelSigADCs.
Bob
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For my design I inted to use a simple counter as a decimator, does that mean PSoC 1 is thr better choice?
Peli
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I am not sure at all.
PSoC5 has tremendously more digital resources compared to PSoC1 and the choice of programming those using VeriLog.
Why don't you start by switching on Creator 3.0 and entering your design. if it doesn't fit switch over to Designer 5.4 and start over. When one of these do fit, get hands on an evaluation kit and continue with the real hardware.
Bob
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Take a look at this for PSOC 1 -
http://www.cypress.com/?rID=2899 AN2041
Pretty easy to mplement basic modulator. And rest of discussion seems to be enough
to handle S/H. a 29466 can handle 16 8 bit counters/timers to 4 32 bit and most variations
in between.
Debugging a little more painful on PSOC 1, you need to have ICE Cube.
Regards, Dana.
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There is a pair of postings from kees about just that:
Modulator: http://www.cypress.com/?app=forum&id=2492&rID=76867
Decimator: http://www.cypress.com/?app=forum&id=2492&rID=76872
For SC/CT primitives see here: http://www.cypress.com/?app=forum&id=2492&rID=76860
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Is this for a product or for your education.
If you are dead set on using a PSoC5 and it is for a product or especially for motor control I would go with a separate ADC like a AD7403. Patching a SigmaDelta ADC together is always noisy and slow and bound to cause problems.