How to read AUTOIN EP(EP2fifobuf) data and send it through RS232?
HELP!
I'm now using FPGA to generate data, write them in 68013 through the slave fifo interface, initial codes like these:
CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
SYNCDELAY;
REVCTL = 0x03; //ENH_PKD=1, out packets edit-able to the core
SYNCDELAY;
PINFLAGSAB = 0x00 | bmBIT7 | bmBIT6; // FLAGB - EP2FF
SYNCDELAY;
PINFLAGSAB |= bmBIT3; // FLAGA - EP2EF
SYNCDELAY;
PINFLAGSCD = 0x00 | bmBIT2; // FLAGC - EP2PF
SYNCDELAY;
IFCONFIG = 0xE3; // b'1110 0011, FIFO clock source out, 48M, clock output enabled; Slave FIFO mode.
SYNCDELAY;
//EP1 bulk
EP1OUTCFG = 0xA0; //b1=1 Valid; [b5,b4]=1:0, bulk;
SYNCDELAY;
EP1INCFG = 0xA0;
SYNCDELAY;
//// out endpoints do not come up armed. Arm EP1OUT endpoints
EP1OUTBC = 0x40; // arm the EP1 OUT endpoint by writing to the byte count
SYNCDELAY;
EPIE |= bmBIT3; // Enable EP1 OUT Endpoint interrupts
SYNCDELAY;
EPIE |= bmBIT2; // Enable EP1 IN Endpoint interrupts
SYNCDELAY;
// EP4 and EP8 are not used in this implementation...
EP2CFG = 0x00 | bmBIT7 | bmBIT6 | bmBIT5 | bmBIT3; //in buffer 1024 bytes, 4x, bulk
SYNCDELAY;
EP6CFG &= 0x7F; //clear valid bit
SYNCDELAY;
EP4CFG &= 0x7F; //clear valid bit
SYNCDELAY;
EP8CFG &= 0x7F; //clear valid bit
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x82; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=1,
SYNCDELAY;
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's
EP2FIFOCFG = bmBIT0|bmBIT3; // AUTOIN=1(bmBIT3), ZEROLENIN=1(bmBIT2), WORDWIDE=1(bmBIT0)
SYNCDELAY;
EP2AUTOINLENH = 0x00 | bmBIT2; // Packet Length = 1024bytes
SYNCDELAY;