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Hi,all
MPEG2-TS------>CY7c68013------>PC
recently,i am doing a job which mpeg2-Ts stream Transferred to a computer.i used cy7c68013a-56 chip,endpoint2 bulk in 4xbuffer.Frimware,i reference to http://www.cypress.com/?rID=39714
my question is:
When I received the usb pass over the data and stores it into a TS file, i found about 1/3 data lost.
Driver: ezusb.sys
frimware:
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48 MHz operation
SYNCDELAY;
REVCTL=0x03;
IFCONFIG = 0xCB; // IFCLK Source internal (i.e.) Gated MPEG_CLK, MPEG_CLK is connected to SLWR
// FX2LP in SLAVE FIFO Mode
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x82; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x84; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x86; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x88; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
PINFLAGSAB = 0x00; //
SYNCDELAY;
PINFLAGSCD = 0x00; //
SYNCDELAY;
PORTACFG = 0x00; //
SYNCDELAY;
FIFOPINPOLAR = 0x04; // SLWR is configured as active HIGH : Can be changed to 0x00 for SLWR to be active Low
SYNCDELAY;
EP2CFG = 0xE0; // VALID - 1,DIR - IN,Type- Bulk, Size - 512 Bytes, Quad Buffered
SYNCDELAY;
EP4CFG = 0x00; // clear valid bit
SYNCDELAY; //
EP6CFG = 0x00; // clear valid bit
SYNCDELAY; //
EP8CFG = 0x00; // clear valid bit
SYNCDELAY;
EP2FIFOCFG = 0x08; // AUTO IN, NO Zero Length Packets, 8- bit Wide
SYNCDELAY;
EP2AUTOINLENH = 0x02; // Auto-commit 512-byte packets
SYNCDELAY;
EP2AUTOINLENL = 0x00;
SYNCDELAY;
OEA |= 0x30;
IOA &= ~20;
I beg your reply......
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Are you implementing flow control on the slave FIFO interface? i.e. not sending data to FX2LP when no buffer is available.
You've mentioned the driver as ezusb.sys? It is not a DMB-T class driver, please clarify how your end application works.
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First of all ,thank you aasi.
I use the upper MFC application, which has been a read thread 。in a loop, reading data...
ezusb.sys as a pc-driver.
Schematic I am using Gated MPEG_CLK.,Already mentioned above(i referenced http://www.cypress.com/?rID=39714)
now, my question is :
when i receive the data and i found a lot of 0x00,0xff.
i looked at the right TS stream, there are 0xff but not the frequency of my high.
I suspect the data is not ready, the top has begun to read the data, leading to my question.
i tried to modigy PKTED,but it doesnot work.
Please give me some suggestions, thanks very much!!!
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sorry,
PKTED----->PKTEND
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Have you verified if the timing requirements of FX2LP have been met on the slave FIFO interface?
Regards.
Anand
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Hi,
Please refer the application notes in the link http://www.cypress.com/?rID=39714.
It just passes the data coming from the demodulator directly to the PC. In the PC/host driver has to take care of the data.
Regards,
Vikas.