Reading QSPI ADS7818 ADC

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Anonymous
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I purchased some QSPI ADCs that I am attempting to use with the PSOC SPI object,

   

http://www.mouser.com/ds/2/405/sbas078-98888.pdf

   

The SPIM_ReadRXData() does not work for some reason. It appears the reason why is the SPI object is not activating upon ReadRXData. According to the datasheet, the ReadRXData only reads the buffer, and does not generate activity on the bus. My scope is not detecting any.

   

Should ReadRXData generate bus activity? If not, how do you read from read only SPI devices like the ADS7818 with the SPI object?

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EvPa_264126
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in the topic    PSoC ® 5> Unusual SAR DMA Results   look   Firmware10.zip    project from kingneb.
This project contains ADS7818_Driver component (verilog).
for clarifications should contact kingneb ....
AD7818/7835 component will be very interesting if it used  4-16  channels (and DMA for write chunks of data in memory).
But while it is difficult for me.

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EvPa_264126
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Excuse for carelessness. I'm getting old (((
I attached the project.
I hope it will help you a bit.
The project does not use SPI. Only PWM and ShiftRegister.
mode: Typical SPI / QSPI Interface Timing.
I tested it with the ADS7818.

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Anonymous
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Here is what I did. I rewrote the verilog object to work in conjunction with a shift register. It appears to be working. Any sugession for improvements?

   

I mainly am puzzled because the load and reset are asserted at the same time?

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Bob_Marlowe
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I cannot see a load-signal in the schematic or in verilog. What exactly are you questioning?

   

When you are talking about the "store" input of the shift register, keep in mind that store is edge sensitive while reset is clock synchron, see datasheet page 2 and 3.

   

Bob

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EvPa_264126
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I see a problem only when the  CLK  and   STORE  fronts s imultaneous, so I added an element NOT to CLK
STORE and RESET shift in any direction relative to each other - no it does not affect the result.
(I tested it like the image below)
However, I do not like the idea of ​​a shift register - it's hard to do 8/16 channels.
I plan to use the Status Register and DMA:
Let's say this:
Inputs Status Register - each connected to its ADC output.
Therefore, the signal CLK we using DMA, can consistently save your bits to 8 channels at once.
After 14-16 cycles DMA memory array can be identified  12 bytes are stored  12 bits of eight channels.
High speed ADS78xx and common to all signal CONV will get data without a time shift.
 

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EvPa_264126
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How do you rate this variant ( 8 channels + DMA )?
I could not find a solution to start DMA at the right time moment.
I just added  a delay for CyDmaChEnable, but I do not like this (

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