9 Replies Latest reply on Sep 4, 2014 10:15 AM by ersic_282706

    ADCINCVR V 4.0 datasheet ambiguity

    ersic_282706

      Hello all,

         

      In the datasheet of ADCINCVR rev 4.0 it says that dataclock is limited to 2.67 MHz  and you can reach 5018sps and it's right if you use 2.67MHz in the formulas. In the previous rev 3.2 the maximum sampling was 10000sps.

         

       

         

      If you take the example project CE54287 which is "Measure and display 0 to 5V on a LCD " the Dataclock is set to 4 MHz. This value is higher than the maximum specified in the datasheet.

         

      If you look at note number 6 it specify a 8MHz dataclock and this note is not referenced anywhere in the datasheet.

         

       

         

      Does someone can explain all this confusion?

         

       

         

       

        • 2. Re: ADCINCVR V 4.0 datasheet ambiguity
          dakn_263916

          File a CASE and let Cypress know there is a documentation error.

             

           

             

              

             

                    

             

          To create a technical case at Cypress -

             

           

             

          www.cypress.com

             

          “Support”

             

          “Technical Support”

             

          “Create a Case”

             

           

             

          You have to be registered on Cypress web site first.

             

           

             

          Regards, Dana.

          • 3. Re: ADCINCVR V 4.0 datasheet ambiguity
            ersic_282706

            Already did!

               

            Wanted to know if someone had the information.

               

            Will keep this post up-to-date as soon as I receive the info from the technical support.

            • 4. Re: ADCINCVR V 4.0 datasheet ambiguity
              ersic_282706

               Cypress gave me a part of the answer. It may go up to 8MHz. For better linearity you have to use it at 2.67MHz and lower.

              • 5. Re: ADCINCVR V 4.0 datasheet ambiguity
                dakn_263916

                Even thats odd. They show in specs 2 Mhz to achieve those specs in

                   

                spec table. But then throw out another value (2.67) and did not clearly

                   

                state what performance you would get. What is it about 2.67 that is

                   

                worth paying attention to ?

                   

                 

                   

                I think the 8 Mhz not unusual, but should have had specs associated with it.

                   

                And then a set of specs attached to the 2.67....

                   

                 

                   

                Food for thought, Dana.

                • 6. Re: ADCINCVR V 4.0 datasheet ambiguity
                  ersic_282706

                   Sorry about it you are right they told me 2MHz

                  • 7. Re: ADCINCVR V 4.0 datasheet ambiguity
                    dakn_263916

                    All these specs come largely from characterization data built up

                       

                    from initial production runs. Hopefully Cypress will update datasheet

                       

                    with, at minimum, data to support spec clock rates.

                       

                     

                       

                    Regards, Dana.

                    • 8. Re: ADCINCVR V 4.0 datasheet ambiguity
                      denniss_46

                      PSoC ADC specs are done at 2.0 MHz because it is the highest frequency where performance can be guaranteed to the specified number of bits  .... and this is important . . . . over all combinations of process variation, voltage and temperature.

                         

                      Most (that's not a quantitative number) of the time, you could run at higher frequency, but Cypress can not GUARANTEE that it will work over P, V, and T. Logically, lower resolution will allow you to run at higher clocks because the opamp settling requirement is not as bad. What falls apart when clock exceeds the power limit are INL and DNL.

                         

                      I requested years ago that we characterize ALL of the ADCs over clock vs resolution vs power. What I came up would have taken several thousand man-hours. This is not practical. There is some useful guidance here. The speed of the opamp varies directly with the power setting, so that an ADC at P=H, B=H and 2.0 MHz clock will have the same INL and DNL performance as P=H, B=L and 1.0 MHz clock. What changes is the data rate.

                         

                      If you need speed and resolution in PSoC1, use the DelSig ADCs. If 10 bits is enough, CY8C28xxx has a 10 bit SAR converter with enough speed to overload the computational pipeline.

                         

                      ---- Dennis

                      • 9. Re: ADCINCVR V 4.0 datasheet ambiguity
                        ersic_282706

                        As is said in AN2239 DualADC and TriADC are both an expended version of ADCINCVR. Those two datasheet specify that the DataClock is up to 8MHz with minor difference in DNL compare to ADCINCVR.

                           

                        I'm not saying that the datasheet of DualADC or TriADC may be used as such for ADCINCVR but that it is ackward that a module that is an extension of the first one allow the user to go higher in frequency.