SPI Slave Hold time violation

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HuEl_264296
Level 5
Level 5
First like given 25 sign-ins First solution authored

I am trying to use the SPI Slave component, but I keep getting Setup / Hold violations. My schematic contains only the SPI Slave component, two DMAs for it, and the necessary digital input and output pins. It is being fed by the Bus clock.

   

 

   

I have tried two different speeds for the bus clock, 24MHz and 64MHz. Both give warnings. What am I doing wrong?

   

Hugo

   

 

   

 

   

24MHz: Hold time violation found in a path from clock ( CyBUS_CLK ) to clock ( SCLK_1(0)/fb )

   

 

   

64MHz:   Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( CyBUS_CLK )

   

  Hold time violation found in a path from clock ( CyBUS_CLK ) to clock ( SCLK_1(0)_SYNC/out )

   

 

   
        
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2 Replies
ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

Consider posting your project, makes life easier to troubleshoot.

   

   

 

   

“File”                                                             Creator

   

“Create Workspace Bundle”

   

Use Firefox or IE, not chrome to post.

   

 

   

 

   

Regards, Dana.

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HeLi_263931
Level 8
Level 8
100 solutions authored 50 solutions authored 25 solutions authored

The SPI Slave component data sheet specifies 10MHz as the maxiumum component clock speed (and 5MHz as the maximum SCLK speed).

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