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I am trying to use the SPI Slave component, but I keep getting Setup / Hold violations. My schematic contains only the SPI Slave component, two DMAs for it, and the necessary digital input and output pins. It is being fed by the Bus clock.
I have tried two different speeds for the bus clock, 24MHz and 64MHz. Both give warnings. What am I doing wrong?
Hugo
24MHz: Hold time violation found in a path from clock ( CyBUS_CLK ) to clock ( SCLK_1(0)/fb )
64MHz: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( CyBUS_CLK )
Hold time violation found in a path from clock ( CyBUS_CLK ) to clock ( SCLK_1(0)_SYNC/out )
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PSoC 3
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Consider posting your project, makes life easier to troubleshoot.
“File” Creator
“Create Workspace Bundle”
Use Firefox or IE, not chrome to post.
Regards, Dana.
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The SPI Slave component data sheet specifies 10MHz as the maxiumum component clock speed (and 5MHz as the maximum SCLK speed).