Attachments are accessible only for community members.
Oct 21, 2014
01:45 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 21, 2014
01:45 AM
I am working on DDS component which would produce two TTL outputs with phase delay between them (it might be useful for lock-in amplifier later). As starting example I use IQ_DDS example posted by PSoC73 a while ago: http://www.cypress.com/?app=forum&id=2492&rID=88149 which based on Verilog DDS code. My dual phase DDS works to some extent (demo project attached), but shows occasional phase flips by 180deg in certain conditions, described below. I suspect that problem in my Verilog code, please advise. Attached below demo project, screenshots and video: http:/youtu.be/qVU3PoVIUxw Video shows that output of two outputs is linearly shifted in cyclical forward <-> backward directions. The phase relationship between outputs behaves as expected while phase is increasing, but there are few 180 deg flips when phase is decreasing. Regards, odissey1
Labels
- Labels:
-
PSoC 5LP
10 Replies
Attachments are accessible only for community members.
Oct 21, 2014
01:50 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 21, 2014
01:50 AM
re-posting due to poor readability: I am working on DDS component which would produce two TTL outputs with phase delay between them (it might be useful for lock-in amplifier later). As starting example I use IQ_DDS example posted by PSoC73 a while ago, which based on Verilog DDS code: http://www.cypress.com/?app=forum&id=2492&rID=88149 My dual phase DDS works to some extent (demo project attached), but shows occasional phase flips by 180deg in certain conditions, described below. I suspect that problem in my Verilog code, please advise. Attached below demo project, screenshots and video: http:/youtu.be/qVU3PoVIUxw Video shows that output of two outputs is linearly shifted in cyclical forward <-> backward directions. The phase relationship between outputs behaves as expected while phase is increasing, but there are few 180 deg flips when phase is decreasing. Regards, odissey1
Attachments are accessible only for community members.
Oct 21, 2014
01:54 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 21, 2014
01:54 AM
Attachments are accessible only for community members.
Oct 21, 2014
01:55 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 21, 2014
01:55 AM
Attachments are accessible only for community members.
Oct 21, 2014
01:56 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 21, 2014
01:56 AM
Oct 21, 2014
02:00 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 21, 2014
02:00 AM
Oct 24, 2014
01:41 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 24, 2014
01:41 PM
OK, I solved the problem.
odissey1
Oct 27, 2014
05:57 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 27, 2014
05:57 AM
Can you tell us about the solution?
Thanks!
Attachments are accessible only for community members.
Oct 27, 2014
10:11 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 27, 2014
10:11 PM
Corrected project attached below. After futile wrecking with Verilog, solution came from old XILINX manual on linear shift registers. I just replaced both Toggle Flip-Flops on the schematics with D-type Flip-Flops for complete sync with the clock (as shown on the picture attached). Alternatively, you may delete flip-flops entirely, which works fine also. I just wander, why PSoC73 put those TFFs in the schematics originally?
odissey1
Attachments are accessible only for community members.
Oct 27, 2014
10:12 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 27, 2014
10:12 PM
Oct 28, 2014
05:29 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oct 28, 2014
05:29 AM
Thanks a lot!