PSoC5LP DDS dual phase component problem

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odissey1
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First comment on KBA 1000 replies posted 750 replies posted
        I am working on DDS component which would produce two TTL outputs with phase delay between them (it might be useful for lock-in amplifier later). As starting example I use IQ_DDS example posted by PSoC73 a while ago: http://www.cypress.com/?app=forum&id=2492&rID=88149 which based on Verilog DDS code. My dual phase DDS works to some extent (demo project attached), but shows occasional phase flips by 180deg in certain conditions, described below. I suspect that problem in my Verilog code, please advise. Attached below demo project, screenshots and video: http:/youtu.be/qVU3PoVIUxw Video shows that output of two outputs is linearly shifted in cyclical forward <-> backward directions. The phase relationship between outputs behaves as expected while phase is increasing, but there are few 180 deg flips when phase is decreasing. Regards, odissey1   
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odissey1
Level 9
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First comment on KBA 1000 replies posted 750 replies posted
        re-posting due to poor readability: I am working on DDS component which would produce two TTL outputs with phase delay between them (it might be useful for lock-in amplifier later). As starting example I use IQ_DDS example posted by PSoC73 a while ago, which based on Verilog DDS code: http://www.cypress.com/?app=forum&id=2492&rID=88149 My dual phase DDS works to some extent (demo project attached), but shows occasional phase flips by 180deg in certain conditions, described below. I suspect that problem in my Verilog code, please advise. Attached below demo project, screenshots and video: http:/youtu.be/qVU3PoVIUxw Video shows that output of two outputs is linearly shifted in cyclical forward <-> backward directions. The phase relationship between outputs behaves as expected while phase is increasing, but there are few 180 deg flips when phase is decreasing. Regards, odissey1   
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odissey1
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First comment on KBA 1000 replies posted 750 replies posted
        screenshots:   
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odissey1
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First comment on KBA 1000 replies posted 750 replies posted
        screenshots   
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odissey1
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First comment on KBA 1000 replies posted 750 replies posted
        Verilog screenshots (posting here is a nightmare)   
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odissey1
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First comment on KBA 1000 replies posted 750 replies posted
        video: https://youtu.be/qVU3PoVIUxw   
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odissey1
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First comment on KBA 1000 replies posted 750 replies posted

OK, I solved the problem.

   

odissey1

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HeLi_263931
Level 8
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100 solutions authored 50 solutions authored 25 solutions authored

Can you tell us about the solution?

   

Thanks!

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odissey1
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Corrected project attached below. After futile wrecking with Verilog, solution came from old XILINX manual on linear shift registers. I just replaced both Toggle Flip-Flops on the schematics with D-type Flip-Flops for complete sync with the clock (as shown on the picture attached). Alternatively, you may delete flip-flops entirely, which works fine also. I just wander, why PSoC73 put those TFFs in the schematics originally?

   

odissey1

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odissey1
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First comment on KBA 1000 replies posted 750 replies posted

Here is updated project

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HeLi_263931
Level 8
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100 solutions authored 50 solutions authored 25 solutions authored

Thanks a lot!

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