UDB access to INTERNAL memory (flash/sram/eeprom)

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Anonymous
Not applicable

Hi There!

   

Only just now discovered PSOCs. The fact that you get a HUGE number of peripherals and canned code is a boon, especially if you can write your own verilog code. Anyway, on to my question:

   

Is it possible to access flash/sram using UDB? DMA seems to only go between SRAM but I'd really like access to that from my verilog code but I have yet to find a function / way to do that.

   

Any help appreciated!

   

 

   

-Mux

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ETRO_SSN583
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Look like answer is no, see 2'ond Q & A -

   

 

   

    

   

          http://www.cypress.com/?docID=31432

   

 

   

You would use DMA/COU to feed SRAM/FLASH data to FIFO's for processing.

   

 

   

Regards, Dana.

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ETRO_SSN583
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Correction DMA/CPU not DMA/COU.

   

 

   

Regards, Dana.

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Anonymous
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 So am I correct in assuming I'll have to use the datapath and a statemachine of sorts in my verilog code to get data in/out of sram and/or flash? (sram will do actually)?

   

SInce I'm a noob on all this (used to doing FPGA's), is the bus arbitration handled automagically or is that something I have to deal with as well. I guess what I'm trying to do is have the CPU write data to a region in SRAM and kick off a process which then munges said data and writes it back, interrupting the CPU when it's done..

   

If it *is* possible, can anyone point me to some relevant information about how to use datapaths? They look nifty 🙂

   

 

   

-Mux

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ETRO_SSN583
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The following might be useful -

   

 

   

    

   

          

   

http://www.cypress.com/?rID=69774     AN82156 - PSoC® 3, PSoC 4, and PSoC 5LP - Designing PSoC Creator™ Components with UDB Datapaths

   

http://www.cypress.com/?rID=69773     AN82250 - PSoC® 3, PSoC 4, and PSoC 5LP Implementing Programmable Logic Designs with Verilog

   

http://www.cypress.com/?id=4&rID=76933     Creating a Verilog-based Component - KBA86338

   

http://www.cypress.com/?id=4&rID=76925     Just Enough Verilog for PSoC® - KBA86336

   

 

   

 

   

Regards, Dana

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ETRO_SSN583
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Basically FIFOs are the Datapath interface to the rest of PSOC.

   

So CPU and / or DMA would be the way to move SRAM data

   

to / from Datapath.

   

 

   

DMA arbitration is implemented in PSOC, see TRM for details, and -

   

 

   

    

   

          

   

http://www.cypress.com/?rID=35180     PSoC® 3 Architecture TRM

   

 

   

 

   

    

   

          

   

http://www.cypress.com/?rID=37793     AN52705     Getting Started with DMA

   

http://www.cypress.com/?rID=82680     AN84810     PSoC® 3 and PSoC 5LP Advanced DMA Topics

   

http://www.cypress.com/?rID=44335     AN61102 PSoC® 3 and PSoC 5LP - ADC Data Buffering Using DMA

   

http://video.cypress.com/video-library/search/dma/     Videos on DMA

   

https://www.youtube.com/results?search_query=dma+psoc Videos on DMA (some overlap)

   

 

   

Regards, Dana.

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Anonymous
Not applicable

 So I guess there's no way to have my verilog module independently read data and the CPU will have to start the transfer. In that case, I *guess* I can have my module create an interrupt which then instructs the CPU to kick off a DMA but that sounds a little iffy...

   

Thanks for all the replies...

   

 

   

Mux

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Anonymous
Not applicable

Hi

   

I am trying to write data on the SFLAH of PROC on CYBLE 02200100 i am successful in wririg to all th four row i have two question here 

   

1)The document tell me that the first row that means row0 of SFLASH will be used to store BLE address ,so does that mean that i cannot use this row for storing any other user data in this row if i am using BLE Component.Although currently i am able to write on all fpur rows and i am not using any BLE component.

   

2)When i do the user protection from FLASH SECURITY  tab in ,cydwr then although i have written protected on these rows still all the new data is written on the lines which i have protected.how to ensure the row protection

   

Niti

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