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I have a resource constrained design, where it would be nice if I could "reverse" several SPI Slaves to be SPI Masters.
Note that there is not enough space to fit both the SPI Slaves/Masters into the design and use multiplexers to the pins.
This isn't bidirectional SPI, i.e. I still have dedicate MOSI/MISO lines, but I would like to reverse them (as well as reverse the drive of the SCK/SS_n lines).
One possibility I had been wondering about is whether I could have a 2nd program on the PSoC's EEPROM that I could soft-boot to, after the first design is complete?
- I don't want to reprogram the EEPROM though, as that would cause too much wear on the erase cycles.
thanks for any suggestions.
A.
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PSoC 3
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I would suggest you to file a "MyCase" and ask if the multi-application bootloader can help you. To do so, at top of this page go to "Support & Community -> Technical Support -> Create a MyCase":
Bob
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Have you consumed all the UDB blocks ? It might be possible to optimize on something else in your design. Can you share your project ? It is difficult to change from slave to master because all the necessary APIs are generated during compile time.
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I've consumed all the sync cells...
I've opened a support case 2707901334.
Looks like I'll go with the dual bootloader approach.
thanks,
A.