creating 50nsec delay with PSoC3 logic cells

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stsm_296211
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I'm creating a range of pulse signals in response to an external trigger (stretching, delaying, etc.) to replace some expensive FPGA functions w/PSoC3 logic cells. I have most in good shape, but need to generate a simple 50nsec delay of the external trigger (an 80nsec pulse), but cannot use any clock based devices due to introduced jitter (ie: counters, timers, SRFF, etc.). With the input pin in Transparent mode, I see about 20nsec delay through any gate (inverter, AN, OR, etc.), but cannot string any together to make that larger. Even adding output pins in between multiple gates, the compiler is too smart and I never see an increased delay. This needs to be done in hardware (ie: no code involved, registers, etc.).

   

Anyone have any tips on creating a small delay in h/w?

   

 

   

Thanks - Steve

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odissey1
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It appears that PSoC creator optimized all logic, so no additional delay can be achieved by adding sequential logic gates. I suspect that it may be possible to trick PSoC by forwarding the external Trigger to another external Pin2, and then reading it back by a Pin3 (this will ba a delayed trigger). If delay is too short (probably ~20ns), add small capacitor in the range of ~100pF between short P2-P3 and the GND.  

   

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stsm_296211
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Yes, that's basically what I'm doing now. I can generate about 30nsec per every 'pin jump' across ports. Trying to create simple pulse/timing generation w/PSoC3 logic cells has been much more problematic than I expected. I thought this would be an easy way to throw away an FPGA on the board, but I'm about ready to just give up and stick with it.

   

 

   

Thanks - Steve

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ETRO_SSN583
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If you simply want to delay a pulse a shift register comes to mind,

   

or a couple of D's wried as a SR.

   

 

   

Also consider using the pulse converter component, see below.

   

 

   

Lastly you can always turn off optimization.

   

 

   

Regards, Dana.

   

 

   

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Anonymous
Not applicable

The delay using capacitors and the logic input thershold would be affected by the temperature, voltage supply and also would be different with a different chip or a different capactor.

   

The digital method suggested would be more stable but would need a high frequency clock to reduce jitter.

   

So how accuray is needed and what kind of jitter is allowed.

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stsm_296211
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 Using a SReg & PulseConverter introduce too much jitter with the 24 or 48mhz clock. I can use those for some of the stretched signals, but I have a couple that need the leading edge to match the external trigger w/no jitter but some delay (like the 50nsec). I need to place the input pin in Transparent mode to again reduce jitter, whicn causes Creator clock sync warnings many clock based components & DFF's as well. SRFF's behave better in this case, and have been usefull to create what I need. But a simple hardware delay is tricky. I can experiment with optimization - good idea.

   

 

   

Thanks - Steve

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Bob_Marlowe
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Steve,

   

you can use a delay-chain with gates (AND, OR, NOT) when you make sure that the optimizer does not reduce the gates downto nothing. This is usually the case when you connect intermediate results to an output pin. I did not try yet if it also works when you connect intermediate results to an n-input OR gate which in turn is connected to a pin, I leave that kind of testing to you.

   

 

   

Bob

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stsm_296211
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 Bob,

   

Yeah, I tried adding an output pin in between each gate (the standard FPGA trick), but the expected delay gets optimized out anyway, even thought the pin o/p's are fine. This may work with non-like logic devices in a chain (ie, don't use 1/2 dozen NOT's, but mix NOT's, OR's, etc.). I like using a n-input gate to an o/p pin idea. I'll try that too.

   

 

   

Thanks - Steve

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Bob_Marlowe
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You may play tricks with a non-registered LUT component using feedbacks.

   

 

   

Bob

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stsm_296211
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 Bob & Dana,

   

You guys were right about the optimizer. Turning the synthesis optimization from exhaustive to off makes the delay predictable with added gates. I took the n-input gate tip too, adding a pin from each gate stage then out to an unused output pin. All adds up nicely. That should do it, as long as the lack of optimization doesn't shoot me in the foot somewhere else.

   

Thanks all - Steve

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ETRO_SSN583
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You could do a quick by setting up a simple test bed where

   

several UDBs are placed. Then check resource use before and

   

after optomization turned off. Will tell you if UDB base is unoptimized

   

before placement or not.

   

 

   

Regards, Dana.

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