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Hi,
I'm using the sample & hold component in my proyect since I need to sample a signald comming from a photosensor which receives light from a very short pulse of light which comes from an LED.
The problem is that when I use the sample and hold circuit I get a noisy signal compared to the one I get when sampling without the H&S.
In my case I'm turing on the LED, activating the H&S with a Control register connected to the clk input of the sample and hold , then turning of the LED and lastly I use the SAR ADC to sample 64 times the voltage in the sample and hold. I'm sampling 64 times to get a better resolution.
When I omit the S&H the signal is good but then it takes too much time for the ADC to make the 64 samples. If I add the S&H it gets very noisy.
I've checked the TRM which in page 271 shows the Track and Hold diagram and it has a hold cap of 12pF and a voltage follower.
If I use the S&H making just one sample at a time it gets a "smooth" signal.
I think the might be that the S&H might not be holding the voltage enough time to do all the conversions.
I've tried adding a unity gain PGA between the S&H and the ADC with the same results.
I'm doing this with a pair of SAR ADCs, Muxes and S&H because I need to sample 10 sensors, 5 on each ADC , and I need to reduce the time the LEDs are on as much as possible.
Does anyone have any idea why this is happening?
Code:
AMux_1_Select ( sensorSelected);
AMux_2_Select (sensorSelected);
CyDelayUs (50); // wait for Muxes to switch
LED_ON();
SH_ControlReg_Write(0); //Start holding and sampling
CyDelayUs (550);
SH_ControlReg_Write(1); //Stop sampling
LED_OFF();
sampleADC (firstLayerSensorOrder[groupLED],firstLayerSensorOrder[groupLED], &sampleTop, &sampleBot);
sampleADC (firstLayerSensorOrder[groupLED]+1,firstLayerSensorOrder[groupLED]+1, &sampleTop, &sampleBot);
Thank you.
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PSoC 5LP
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Can you post your circuit diagarm and upload your project, it would be easier to check
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Consider posting your project, makes life easier to troubleshoot.
“File” Creator
“Create Workspace Bundle”
Regards, Dana.
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The SAR ADC can run with a sample rate of up to 1MSps, that means it could sample 64 times in 64µs. Does the signal on your photosensor really change that fast?
Regarding the S&H: I assume from your description that the control register is connected to the SCLK input of the S&H. Then the S&H samples directly at the first write, since it does so on the falling edge of its clock input (except when you configure otherwise). Or did you configure it as Track&Hold? (If yes - why?)
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One question: how do you determine that the signal is noisy?
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Hi,
Sorry for taking so long, I've been very busy and also trying to figure out this problem.
I've attached the schematic in PSoC and the signals I receive (Left when not using S&H, Right when using it).
The signal comes through a 1K resistor from a light sensor TSL257: http://www.ams.com/ger/content/download/250427/976469/file/TSL257S_Datasheet_EN_v1.pdf
I've also tried using a 0Ohm resistor.
I've tried using Sample and Hold, and also Track and Hold I get somewhat the same results.
I'm sorry but I can't post the project.
I think that it might have something to be with the noise in the system and the fact that I'm making many samples for each "sample" is integrating them and "reducing" the noise.
What do you think?
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You did not supply us with *ALL* information to check. As Dana said, better is to post the complete project here.
I would think that there is some time needed between the settling of the S&H and the start of the ADC which should not run continuosly. I would suggest to use a PWM or something equivalent to generate the timing for LED, S&H and ADC.
Bob
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You can run the A/D continuosly, simply throw away the first sample
after a mux / S/H change.
Regards, Dana.
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Hello Bob and Dana,
I'm not running the ADC continuosly and I can't use a PWM to sincronize the LEDs, ADC, and S&H since I'm controlling many 8 LEDs with a LED driver TLC5922.
I've tried already to leave some time between the S&H and the ADC conversion and I get the same results.
I seriously think that the noise I'm getting is the noise from the system, since theorically I'm having a not so good 15 bit ADC with a Vref of 2.048V, so I'm having about a 20mVpp of noise which doesn't crazy for the system and the pseudo 15 bit ADC. I guess that when not using the sample & hold I'm integrating several samples which acts as a low pass filter.
What do you think?
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So with "noise in the results" you don't mean you are getting noise in the reading for one S&H operation (so all the 64 measurements taken from one sample are about the same), but you are getting noise when looking at the results from different sample operations?
If yes, than you might be right - taking many samples will act as low-pass filter.
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Exactly, I see the noise when plotting the different samples in time.
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Yes, then you did not see that before since taking multiple samples will reduce the noise. So I think your best option is to remove the S&H and use the SAR ADC to take multiple subsequent samples (maybe by utilizing the DMA, so the CPU is not involved).
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If you have a DSO set it to infinite persistence and look at your signal
in pin with a DC value on it. That will give you peak to peak noise. If
you look at Vdd you will typically see several hundred mV of noise,
much of this will show up in ground bounce, hence your 16 bit ADC
looks like << 12 bits.
Use polymer tants for bulk bypass, they have an order of magnitude better
Z vs F then regular tants. And as always .01 uF cermaic in parallel. Look
carefully at datasheets not all capacitors same, even speced at same farad
level.
If noise is uncorrelated (not necessarily true in a UP application) then
averaging works.
Regards, Dana.
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Hi,
Thank you all for your help.
I just wanted to let you know that it was just what I was thinking. The noise is there I was just integrating it with the multiple samples when not using the S&H.
Thanks Dana for the advice. I managed to reduce the noise to a workable level for us.
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The one other thing you can do is implement a S/H yourself
with one of the OpAmps and an external cap and analog mux.
That would allow you to use a bigger cap, as the onboard S/H cap
is pretty small. That would help with noise. Downside is acquistion
time would increase, but hold time would also improve. Several
tradefoffs.
Regards, Dana.
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Thanks Dana,
I thought of doing that but that means changing the board and right now is not a possibility.