Anonymous
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Jan 07, 2015
01:43 AM
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Jan 07, 2015
01:43 AM
Hi,
in our project we are using a self developed core using some datapaths. FIFO is disabled through AUX registers (CLR bits are set) to minimze delay.
Will the content of F0/F1 be overwritten with rising signal on f0/f1_load, even if the content wasn't read before? Again: FIFO is in single buffer (= register/latch?) mode.
From my obersavtion I have to first read F0/F1, than the UDB can write a new actual value. Is this correct?
Reagards,
Franz
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PSoC 3
2 Replies
Anonymous
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Jan 08, 2015
11:16 PM
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Jan 08, 2015
11:16 PM
Hey,
You can check the "Component Author Guide", Page 56. (PSoC Creator -> Help -> Documentation -> Component Author Guide).
It says, "
Single buffer mode –
This mode configures the FIFO to be a 1-word deep buffer instead of the normal 4-word deep FIFO. Any value written to the FIFO immediately overwrites its content. This mode can be used if only a 1-register FIFO with its corresponding FIFO bus and block status signals are needed"Thanks,Keerthi
Anonymous
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Jan 08, 2015
11:27 PM
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Jan 08, 2015
11:27 PM
Sorry, its page 46