Anonymous
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Sep 15, 2013
12:59 PM
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Sep 15, 2013
12:59 PM
Echo clocks (CQ and /CQ) are not truly differential signals. They are single ended signals which are 180 degrees out of phase .So, we need to route these signals as single ended but we need to ensure that, both should have minimum skew with respect to each other. K and /K clocks are also not truly differential clock signals. Please note that there is no differential receiver in the SRAM. The memory uses the rising edges of K and /K to latch input signals. Both clocks are single ended signals. Although they are not truly differential, it is advised to keep K and /K 180 degrees out of phase with respect to one another. Also please note that there is no special requirement to route CQ and /CQ and K and /K close to each other, however trace characteristic, length should match so that there is no skew between them. Since in this case it is pseudo differential clocks, rising edge of one clock and falling edge of the other clock should match and there should not be any skew between them.
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3 Replies
Anonymous
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Sep 15, 2013
01:03 PM
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Sep 15, 2013
01:03 PM
We don’t have any differential receiver in the SRAM. We have all the comparators at the input of the SRAM which compares the input with Vref. If the SRAM has ODT feature on K and /K inputs, we can also enable the On-Chip Termination Resistor on these pins and you can route the signals as single ended.
Anonymous
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Jan 27, 2015
03:38 AM
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Jan 27, 2015
03:38 AM
Hi,
You write that CQ/CQ# and K/K# are not truly differential signals. Must these traces be routed to have 50-Ω impedance and should be kept away from each other (for example CQ from CQ# and K from K#) to a minimum of 5x the trace width (AN4065)?
Anonymous
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Mar 02, 2017
04:12 AM
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Mar 02, 2017
04:12 AM
Does this ruling of pseudo differential clocks for K/K# or CQ/CQ# hold true even for QDR-II+ Extreme ?
I have CY7C2565XV18 daughter cards and I am using single pin of rx clock i.e. CQ as reference clock to generate phase shifts 90deg in clock internally to align to incoming data Q in my FPGA design. Is this correct way ?
Thanks & Regards,
Shafi