Looking for a firmware example using four endpoints (Sync. FIFO on a FPGA)

[Anonymous]

     Hi!

           

For our design using a FX3 I am looking for a FX3 firmware example using 4 endpoints.

   

The GPIF II interface is used as a sync. FIFO interface were the FPGA is the master.

   

The GPIF designer contains a predefined project for this. (sync_slave_fifo_2bit)

   

The SDK also has a predefined project (SlaveFifoSync), but it seems to only support two endpoints.

       

Is there a firmware example using four endpoints?

   

Or is the predefined project easily adapted by just creating two additional endpoints?

       

With regards,

   

Jacob

[Anonymous]

You can easily modify the SlaveFifoSync example to incorporate two additional endpoints.

       

These would be the required changes:

   

-- In the cyfxslfifousbdscr.c file, ddition of two endpoint descriptors. Also update the bNumEndpoints field in the Interface descr and also the total length field of the Config descr.

   

-- In the cyfxslfifosync.c file, look at the CyU3PEpConfig_t structure and change it as per your requirement and configure your two endpoints using the CyU3PSetEpConfig() API.

   

-- In the cyfxslfifosync.c file, create two additional DMA channels using the CyU3PDmaChannelCreate() API call. Make sure to give unique values to the producer and consumer socket ID's. Sockets cannot be reused across multiple channels.

[Anonymous]

Hi!

       

That sounds as simple as it should be ...

   

I already thought is something like that, but nice to be sure.

   

Thanks for the reply.

       

With regards,

   

Jacob