2 Replies Latest reply on Feb 3, 2015 3:55 PM by PrMa_264311

    Mixed SRAM and FLASH EMIF


      I would like to add 128Mbits of NOR flash and 16 Mbits of SRAM into a graphical LCD project (800x480 pixels). They need to share the same address and data bus due to the limited number of pins available on the PSoC5LP. This memory and storage expansion is necessary because of the larger graphics files. The PSoC5 simply doesn't have enough resources on chip to handle the graphics files.


      In order to make this fly, it is necessary to find SRAM and FLASH that can live comfortably on the same bus. I'd like to just use the EMIF interface to handle all transactions. I've looked around a bit, but I haven't found any NOR flash chips that allow for simple reads and writes. Surely there must be because the EMIF datasheet seems to imply compatibility with NOR flash (no mention of needing to use a custom interface).


      Has anyone had luck in a project trying to do this? Any suggestions on candidate RAM and FLASH chips?





        • 1. Re: Mixed SRAM and FLASH EMIF

          Did you consider to use I2C interfaced memory? This would use only 2 signals to connect. Cypress has got an FRam memory with 256kByte capacity and may be red/written with up to 1MByte/s.


          To get quickly hands on this you may order a BLE development kit that has got one of these FRam chips on board, have a look here: www.cypress.com/





          • 2. Re: Mixed SRAM and FLASH EMIF



            I had considered using a SPI/SRAM setup similar to what you mentioned. The trouble with it is moving data out of FLASH to the working buffer in time. Ideally the response time would be quick. SPI alone would not be fast enough. SPI FLASH utilizing quad-speed technology would be fast enough, but would require some sort of custom hardware interface.


            Here is an illustrative example of what I'm up against. Assume I wanted to send a full-size bitmap to the screen with each user interaction. Think of flipping through images on your smart phone. Each screen (at 24 bits per pixel) would require 1.15MB of data transfer. A Spansion 512 Mbit S25FL512SAGMFI011 SPI could hold the images. The PSoC pins are limited to around 33MHz signalling rates. Neglecting overhead and assumming I could really hit a 33MHz signalling rate with the on-board SPI hardware, a single image would take 280ms to transfer. That is a noticable and annoying delay. If I used the quad speed (custom hardware), I could decrease it to around 70ms, which is doable.


            Of course the better way would be to load all the images into RAM and work directly from there. That just creates a delay at the beginning, which is what I may have live with.