Use memory in Verilog component.

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Anonymous
Not applicable

 Hi. 

   

 

   

I'm trying (for now) write easy verilog components for my Master Science thesis, and while making short LIFO stack I have problem, because: "Build error: memory declaration is not supported"

   

Is there anyway to avoid this problem, for example, can you use somehow RAM build in PSoC 5LP, to make this component possible?

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ETRO_SSN583
Level 9
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Consider posting your project so forum can take a look at it -

   

 

   

    

   

          

   

“File”                                                             Creator

   

“Create Workspace Bundle”

   

 

   

 

   

Regards, Dana.

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Anonymous
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 I don't think that this will be needed.

   

I just found in Verilog Warp Guide: "Arrays of register data types (memories) are also not supported in Warp."

   

Now I only have question in my second part of my 1st post. Is there any (easy) way to connect component, written in verilog, to RAM built in PSoC?

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odissey1
Level 9
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I think that only connection between hardware (Verilog) and CPU (RAM) is through the Register component (which you can find in Cypress tutorial movie).

   

odissey1

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Anonymous
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 If it is only way to do this, could you send me link to this movie.

   

I can't find it anywhere.

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ETRO_SSN583
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Go here and search for “verilog” and “datapath”.

   

 

   

http://video.cypress.com/video-library/?source=CY-ENG-HOMEPAGE&medium=Body-Support

   

 

   

Regards, Dana.

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Anonymous
Not applicable

 How using Datapath would help me to make memory in verilog component?

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Bob_Marlowe
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Because the DataPath object

   

has got 2 FIFOs

   

can be accessed by DMA

   

has got registers to write to and read from

   

and last, not least has got an ALU

   

 

   

Bob

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odissey1
Level 9
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First comment on KBA 1000 replies posted 750 replies posted

@Piotrbov,

   

if succeed, please post the final project so we all can benefit, there are scarce examples on Verilog in PSoC available so far.

   

odissey1

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