Delta Sigma Noise

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AlVa_264671
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Hi Every One !

   

 

   

I would need some help regarding noise generated for the Delta sigma in single end configuration.

   

As you can see in the schematic as result of array scanning I am geting pulses which votage depend of the pressure applied to every cell in the array.  My Vdda is 3.3 v . The issue is that with no pulse, ( checked with osciloscope) there is noise that  you can watch in the graphic display picture.

   

The only way to avoid that is using a PGA before the Delta sigma..

   

I cannot undestan that. !!!!

   

And even using a PGA,  I need to filter trough  code , like high pass filter values above 0x80, wich represent almost a half of the ADC range.

   

I woul appreciate very much any help.

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ETRO_SSN583
Level 9
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It would be helpful if you posted your project. Note you mentioned something

   

attached but there is nothing present in your post.

   

 

   

At high resolution layout, bypassing critical to getting noise floor capability

   

as shown in datasheet. These may help -

   

 

   

    

   

          

   

http://www.cypress.com/?rID=39677     AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations

   

http://www.cypress.com/?rID=40247     AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations

   

http://www.cypress.com/?rID=39974     AN58304 - PSoC® 3 and PSoC 5LP – Pin Selection for Analog Designs

   

 

   

    

   

          

   

http://www.cypress.com/?rID=43337     AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations

   

 

   

 

   

Consider the following when at hi res -

   

 

   

1) Shut off all digital I/O on pins adjacent to A/D inputs, also consider

   

stoping UDB resources to minimize internal ground bounce and coupling

   

2) Set Vref to external bypass, use a polymer tant to bypass it.

   

3) Simple averaging helps noise reduction

   

4) Using specturam analyzer determine noise source by its signature

   

 

   

Regards, Dana.

   

 

   

    

   

          

   

Consider posting your project, makes life easier to troubleshoot.

   

 

   

“File”                                                             Creator

   

“Create Workspace Bundle”

   

 

   

Regards, Dana.

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AlVa_264671
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AlVa_264671
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Thank you Dana  for your help!

   

 

   

It's seem to be that it cannot be uploaded  my pdf where I show you my schematic.

   

I tried to upload twice.

   

I will try again.

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AlVa_264671
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        I will try with Google Chrome   
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ETRO_SSN583
Level 9
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Route your Amux output to a pin, do you see 7 Mhz  clock transients

   

on it ? I would posit the reason a PGA suppresses transients is because

   

of its slew rate limiting effect, eg. it acts as a LPF to edge transients like

   

clock feedthru in a CMOS switch.

   

 

   

Regards, Dana.

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AlVa_264671
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Thank you Dana !!!

   

May be I cannot understand you complletelly.

   

I undestand that you said a bout PGA acting like a filter .

   

But , what do you mean saying tp pass the Amux output trough a pin ?

   

On the other hand,  If I put  ociloscope's test point at resistance of 2.2 k which is hooked up to pin 3[3] and there is no  array cell touched, there are  information going to the dipaly like random noise even when you cannot see any signal on the osciloscope.

   

 

   

Tnak you very much Danna

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AlVa_264671
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Hi there !  are there some other input for my question?

   

Thank you all of you.

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ETRO_SSN583
Level 9
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You accomplished what I stated by connecting your scope to the

   

2K R at the output of the Amux. The idea was to observe the noise

   

at the A/D input from the Amux output at a pin.

   

 

   

Do you still get a lot of noise when you short the 2K R to ground, therefore

   

making A/D input also ground ?

   

 

   

Best would be to post a project archive as I discussed earlier.

   

 

   

Regards, Dana.

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ETRO_SSN583
Level 9
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Are you setting your reference to allow for external bypassing ?

   

 

   

   

 

   

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