GPIF-II Master example project not working

[Anonymous]

    Hi,   

       

    I am looking at the example project of GPIF-II Master downloaded from     http://www.cypress.com/?rID=84236 .   

       

    I tried simulating the timing diagram on GPIF-II designer and it gives me error for WRITE operation (data from master to slave) in transition of WR_DATA_WAIT to COUNT_HIT saying invalid state machine path, see the attached picture.   

       

    I didn’t change anything and just made a timing scenario on GPIF designer with sequence of   

   

     START →     RD_WR_IDLE →     WR_FLAG →     WR_DATA →     WR_DATA_WAIT →     COUNT_HIT →     RD_WR_IDLE.   

       

    It didn’t give errors when I simulate it until WR_DATA_WAIT, as soon as I added COUNT_HIT it shows the error.   

       

    However, the project was built successfully (without changing anything). Is the state machine still gonna work despite the error? Is the WRITE operation gonna work?   

       

    How can the error be solved?   

       

    Could someone from Cypress explain why this is?   

   

    If anyone have any idea, would be greatly appreciated..   

       

    Thank you very much!   

           

    Regards!   

[Anonymous]

Hi A.K,

   

In the state machine, you can see that the LD_DATA_COUNT and LD_ADDR_COUNT are set to 2047 and 255 respectively. This means that DATA_CNT_HIT (data counter hit) becomes valid only when Address Counter is counted and hit 8 times. So, WR_DATA_WAIT -> WR_DATA and back to WR_DATA to  WR_DATA_WAIT should take place 8 times for the ADDR_COUNT to hit. (Note that WR_DATA state performs both COUNT ADDR and COUNT DATA operations). 

   

In the Timing scenarion you created, you just do this once and want it transition to COUNT_HIT state which is reached only when DATA_COUNT is hit.

   

That is why the error was thrown.

   

Regards,

   

- Madhu Sudhan 

[Anonymous]

Hi Madhu Sudhan,

   

The DMA buffer size is 16×1024byte and ADDR_CNT_HIT when 1024byte data transfered.What is DATA_CNT_HIT counter use for?

   

Thanks,

   

-Ran Liang

[Anonymous]

    Hi Madhu Sudhan,   

           

    Thank you! didn't notice WR_DATA does count address and count data!   

       

    But now I encounter another problem. It hits ADDR_CNT once, but I couldnt transition from WR_DATA_WAIT to WR_DATA again since the DMA_RDY is not asserted.   

       

    Is there a way to assert the DMA_RDY flag by force?   

       

    Thanks and regards!   

       

[Anonymous]

 Hi A.K,

   

You cannot assert it by force. Sorry for inconvenience.

   

For testing purpose alone, you can remove the DMA_RDY_TH0 from the transition equation and do the timing simulation.

   

Regards,

   

- Madhu Sudhan

[Anonymous]

Hi Madhu Sudhan,

   

Thanks! It simulates fine now without DMA flag. I also tried with IN_REG_VALID which simulated also fine..

   

Regards!