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Hi there,
I'm Nuno and I've just started to play with PSoC 4, first time on PSoCs. Just wanted to say Hi and leave my 1st PSoC project, which I called "programmable infinite resolution triangle wave generator". Big name, uh :)?
It's a remake of the traditional analog capacitor based opamp and voltage comparator triangle wave generator, but this time the charging and discharging of the capacitor is under digital control. You have the "pure analog" output but can control frequency, and this can make it to at least 245KHz in 1KHz steps. It needs calibration because as the frequency goes up the time spent in the comparator ISR influences more and more the output amplitude/frequency, but the relation is linear; with the calibration values on the source code it generates a wave of nominally 10KHz .. 245KHz in 1KHz steps, 1Vpp, 120mV offset.
This was made with the prototyping board, so you have the bootloader in there. I noticed that once a PC application opens the serial port you have a kind of crosstalk between the comparator's output and the opamp's output.
If you have any feedback or just want to say hi, don't be shy :)!
Cheers!
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NJAY, welcome in the fascinating world of PSoCs and congratulations for your first project!
Thank you for sharing it with us.
Bob
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Very nice design, I like your approach. Some thoughts -
1) Add a open drain output to rapidly discharge cap to create a SAW/RAMP waveform
2) ISR creates jitter, possibly use module editor and create a hard wired connection
from comparator out to IDAC polarity register
3) Consider diode or JFET waveshaping to generate sine from triangle
4) Bring comparator output to a D F-F to create square wave
5) Add counter to count waveform cycles, to effect a burst of N cycles and then stop
Regards, Dana.
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... and for the overdone blinking dimmed LED:
Use an 8-bit UDB-based PWM and an 8-bit PrISM (UDB-based,too). This will use 2 of the 4 USBs and saves your TCPWMs.
Bob
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Or save your UDBs, as they are more general, and stay with
the approach you are now using. But following applies for
APIs
FLASH SRAM
TCPWM 1020 2
UDBPWM 524 13
Regards, Dana.
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Thank you everyone for the welcome.
My thinking of the overdue dimmed LED blink is that the modulation should be done in sw thus using only 1 PWM machine while serving the purpose of telling the "guy outside" that the sw is still running 🙂 . But I was just experimenting; as it is, it's only an aesthetic feature.
1), 3), 4) and 5) would give a function generator, wouldn't it Dana :)? Of course it has crossed my mind, but 245KHz triangle wave is just too little to make a FG I would have use for.
Now, 2) is very interesting, can you do that in PSoC4? I totally missed that and it is the ISR that limits the frequency so, if it can be done in hw, that's a whole new level! It's not that easy as connecting the comprator's output to the polarity bit, but can surely be done. Any hint on how to connect a hw line to a configuration register? I can't find any component that looks like it could do that.
By the way, was it just me that noticed that there are missing bits on the documentation for the IDAC related registers of PSoC 4? For example, the polarity register/bit is not documented (PSoC® 4 Registers TRM document, latest I found is from 25 Jun 2013), although you can just look at the code generated by the Creator and get that info from there.
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I can't see anything in the datasheet that even hints at the possibility of having the hw control configuration registers, are you sure that can be done in PSoC 4?
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I was thinking of using module editor to create custom module or
verilog to accomplish that.
You are right, limited Fgen, but then it covers audio, ramp rate would be good
for testing power supply startup behaviour......so could be useful.
Regards, Dana.
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Well, the thing is, on PSoC the IDAC registers are not writeable from the hw (it is stated in the registers manual).
And to re-create that in programmable logic doesn't seem possible to me (without much external hw), because of the IDACs.
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I meant "on PSOC 4" above.
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Looks to me like it could be done via CSD_IDAC registers ?
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Right... and how would you connect, let's say, the low power comparator output to the idac polarity bit in one of those PSoC4 registers? I've looked at the Creator components, went through the datasheets and I'm totally clueless.
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So I've been thinking again about this and came to a design that can generate the triangle wave to higher frequencies and fully done in hw. On the original method the IDACs configuration need to be flipped in sw, and this handling (in an interrupt) is the frequency bottleneck. With optimizations (direct register use, other) I was able to generate a 1Vpp 245KHz triangle wave, keeping the CPU near 100% usage. Using this new method I can generate a 0.48Vpp 1MHz triangle wave without any CPU intervention. The top peak gets quite some distortion and some applications I think the ramps may still be usable. I haven't yet refined it, it's still just a proof-of-concept but here it goes the schematics. Anyone care to especulate on how does it work :)?
Cheers
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Would you mind posting the project archive, I would like to take
a look at it.
“File”
“Create Workspace Bundle”
Use Firefox or IE, not chrome to post.
Regards, Dana.
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Yeah, here it goes. This is the proof of concept version, meanwhile I improved it a little bit, turned SSMux into a switch which is "transparent" and therefore no more jitter from sync with HFCLK, but that version is still too convoluted to publish.
Cheers
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Hello Dana,
i am interrested in this last version code posted from Njay. It generates a triangle wave. It was built with PSOC 4 can you please help me built it for PSOC 5. I have tried without success.
When i built the program i received this messages:
Signal "Net_2176" is expected to connect to only one GPIO analog pin but instead it connects to "\IDAC8_1:viDAC8\". Please fix the connection.
AMuxHW (Hardware Amux) only supports controlled analog connections to GPIOs. Please make sure all the controlled analog connections are connected to GPIOs.
Thank you for replying.
Regards
Rosine
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I assume you started a new project in order to remove all PSOC 4
related component stuff. Can you post that project and forum will take
a look at it. I assume it also will have boot loadable setup removed
from it.
One other issue, unlike a table driven approach Njays approach requires
AGC in the loop to get a fixed amplitude signal. You could differentiate the
ramp and use that in an AGC loop that controls a FET as a variable R to
implement AGC. So there is more complexity than immeadiately apparent
in the design. Food for thought.
Regards, Dana.