If you have a high Z pin connected to logic internally,
and leave it floating, then tie a R to ground (or Vdd), and
size it such that worst case leakage does not create a legit
undesired logic level.
Another way is no R, disconnect pin with a register write, and
ignore it. However that is not ideal as the pin could reach a level
where input buffer N and P MOS are both turned on, drawing a
lot of current in the totem pole. Its also not ideal becuse now the
internal route is floating.
exactly as I was thinking, but good someone with more exp. to verify it.
One thing, which still baffles me is the high-impedance part.
I measured the impedance on the cable coming from the external machine, it is 25ohm.
Not possible to meassure the resistance of the pin on PSOC side !?
However, there is internal resistor for pins configured as pull up/down digi input, but it seems there is no high-impedance resistor for digital high impedance input pin !? At least it is not shown on the overview schematic in PSOC Creator. I can also assume there is none, otherwise I would not have the effect of easy flipping when pin left hanging.
If I connect 1 Mohm in serial, the schematic is not working anymore. So who is taking care of the high impedance ?
High impendancce is absence of a resistor an only leakage on the pin. No guaranteed input current min, only max.
When something does not work as expected you may upload your complete project here so that we all can have a look at all of your settings To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
To put it the other way round: High-Z / High-impedance input pin means that the pin itself has a high impedance (so it doesn't put any load to whatever is driving it). It does not mean that the pin can be driven by a high impedance driver - and a 1MOhm resistor is a high-impedance driver.
What happens in that case depends on many circumstances - how much impedance the PSoC pin presents in the current situation and how big the driving impedance is. E.g. when the actual input resistance is 1Meg, and you drive the pin with a 1Meg resistor, you have effectively a resistor divider cutting the voltage in half.
Btw: impedance is not only the resistance of the cable you have connected, but also the impedance of the circuit driving that cable.
If you have a pin that is in Hi Z, but you do not want the pin and its connection
to create an illegal logic level, then terminate it with some level of DC resistance.
So for example if leakage spec at worst case temp is 1 uA, and you terminate it with
1M ohm, then potentially it will either be at 1V from the rail you terminated to. In 5V
CMOS that implies you have achieved a 'legal" logic level.
An example is if you where driving the gate of a power MOSFET, and the pin driving
the gate was, for what ever reason, put into HiZ a R to ground would absorb the leakage
and keep the MOSFET off.
Do NOT place a 1M in series with the pin and its load, that destroys the AC performance
of data in/out of GPIO pin. Typical Cin is 5 pF, so 1M and 5pF = 5 uS, so 5 x RC is 25 uS or 40 Khz,
so rise/fall times horrible.
HiZ means both N and P MOSFETS in the driver pinched off, then result is just a leakage
component of unknown sign, can be source or sink, no predicting. Also if you config a pin
to be HiZ analog in, and your source for the pin is also high impedance, the pin is very
subject to noise pickup due to C coupling. Sometimes HiZ can be a blessing, other times
a curse. In the latter case you drop the Z to minimize noise impact, but then you sacrifice
power by doing so.