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Hello,
I'm a beginner on PSOC, and i'm trying to understand ADC et DAC components on PSOC Designer.
Then i put a ADC and a DAC completely opposite for having the same input signal and output signal.
But after doing all adjustement, I don't get the same signal.
I need some help
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PSoC 3
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If you set ADC resolution to same as DAC you will still have a small
amout of error between the two readings. Are you comparing binary
result from ADC or converting to V, same for DAC, then comparing ?
You have to look at what the read returns on ADC, sign or unsigned,
reference, and do the converison.
Post your project archive and forum can take a look at it.
"File", "Archive Project", do not use chrome to post.
Regards, Dana.
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One other contributing factor, if using PGA feeding ADC (from datasheet) -
The input and output voltage ranges of the amplifier do not extend to the power supplies
(i.e., they are not "rail-to-rail" opamps). The allowed input range is a combination of input
limit, output limit, power supply voltage, analog ground value, and selected gain. This is
illustrated in the DC and AC Electrical Characteristics section.
Regards, Dana.
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As an aside you posted in PSOC 3 forum, which uses Creator tool, not Designer.
If you are in fact PSOC 3 then using ADC with input buffer disabled will give you R-R
performance. The PGA is R-R in PSOC 3, although allowed inpout swing dependent
on G you use.
Regards, Dana.
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I think I have perfectly configure the PGA and the ADC.But I have some difficulties to configure the DAC, then i just have noise on DAC output.
Do you have a few time for consulting my software andtell me exactly where i'm wrong or correct it?
PS:For the next time, where do you publish my answers?
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"PS:For the next time, where do you publish my answers?"
Stay with this thread for now.
Go ahead and post project archive and Forum will take a look at it.
Regards, Dana.
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Here is the project.
Thank for your support
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The project you posted is incomplete. In Designer go to "File",
"Archive Project", and post that zip file.
Regards, Dana.
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Justr started looking at project, change -
1) Global properties, upper left window, A_Buff_Power, Op-Amp_Bias to high power.
Regards, Dana.
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The DAC data value should be set to offset binary, as you have
set the A/D to unsigned.
You want to decimate by 32 to achieve 8 bits to match DAC, so
set PulseWidth in CAN properties to ( 4*n -1 ), n = decimation rate,
so set PulseWidth to 127.
Global properties, set CPU_Clock to sysclk/1
Regards, Dana.
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Change this line of code to -
if ( CAN_fIsDataAvailable() > 0 ) { // attente que la donnée issue du CNA soit prête
Regards, Dana.
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Last change your global properties VC1 to a divisor of 8, so that you
can meet DAC max clock rates.
In general when you place a module, look at datasheet, it covers each
property. Additionally it covers each API, what it does, and what it returns.
And global properties, always examine those to make sure you are set
up correctly. Same with analog column clocks, they must meet the clock
rate of modules in that column. Adjust VC1/VC2/VC3 for clock rates to compo-
nents that use them.
Regards, Dana.
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I do all the changes you ask me to do (thank you by the way).But when I want to digitize at 40 kHZ, I just have noise.
I think there is a problem with the clock of the DAC.
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You have your globals set up as below ?
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Set VC1 in global properties to 3 to yield an 8 Mhz column clock, max
DelSig freq, which should yield 60K+ SPS.
Then slow the DAC clock down by using either VC2 or VC3 and change their
dividers to get a clock you want. Look at ratings in datasheet for performance.
A slower clock should decrease noise.
Note when you write to DAC, do not write a value > 254 per datasheet.
Regards, Dana.
Prior post did not show all, attached are global settings, but per comments above change
DAC clock, VC2/VC3 whichever you decide to use.
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I did a test of the DAC noise, and got the below.
You can see some noise, simple RC might be able to eliminate most of
it.
I used offset binary for data format property. And following simple code.
Running at ~ a write rate of 80 Khz.. Clock to DAC set at 3 Mhz.
unsigned char seedvalue = 0;
PGA_1_Start( PGA_1_HIGHPOWER ); // Démarrage du PGA -- Mise sous tension
CAN_Start( CAN_HIGHPOWER ); // Démarrage du CAN -- Mise sous tension
CNA_Start( CNA_HIGHPOWER );
CAN_StartAD( ); // Démarrage de la conversion
M8C_EnableGInt; // boucle infinie
while ( 1 ) {
// if ( CAN_fIsDataAvailable( ) > 0 ) { // attente que la donnée issue du CNA soit prête
//
// valeur = CAN_cGetDataClearFlag( ); //chargement de la donnée convertie dans "valeur"
// CNA_WriteBlind( valeur );
// }
seedvalue = ( seedvalue < 254 ) ? seedvalue + 1 : 0;
CNA_WriteBlind( seedvalue );
}
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Almost forgot, the clock phase property of DAC set to "normal", not
"swapped" as you had before.
Regards, Dana.
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Welcome in the forum.
This thread really is an old one and your question goes into the wrong forum. Here we are for PSoC3 and you ask for a PSoC1.
I would suggest you to create a new thread in the PSoC1 forum to have the Gurus see your question.
Bob