According to the die-level schematic for the 20732S (version SB03 that's shipping), the Pin 37 of the device is affiliated with port GPIO:P24 (the 20732S TRM Page 13 states this too).
The 20732 SOC Datasheet states GPIO:P24 is the Peripheral UART TX line (aka PUART_TX).
Perhaps the author was trying to remind people that the 20732S TX line should attach to the the RX line of whatever is hanging on that port?
The TRM should probably remove the "(PUART_RX)" nomenclature.
If you look at Pins 35 and 36, these list the alternative functions as <noun name> then <firmware/SW understood name/identifier>, so this would lead me to believe that this is a typo.
I will confirm with the technical team then create a ticket with our tech pubs group to update both the 20732S and 20736S datasheets if this is the case.
I confirmed that this is a typo and Peripheral UART TX(PUART_RX), should say Peripheral UART TX(PUART_TX).
I will work with our tech Pubs group to update BOTH the 20736S and 20732S datasheets.
Thanks for pointing this out.
The datasheet for the 20732S has been updated to correct the typo for Pin 37 noted above: CYW20732S Bluetooth Low Energy SiP Module Technical Reference
The 20736S datasheet will be modified as well since the two are identical from a HW perspective.
Why the I/O type of pin 37 is still "Input" while it is a peripheral UART TX?!?
Could you check the data direction (I/O type) for all the peripheral UART pins (P0, P1, P2, P3 and P4) please?
Per the Hardware Interfaces Guide here, page 23: WICED Smart Hardware Interfaces
The BCM2073X supports up to 40 GPIOs. The majority of these GPIOs have multiple functional modes (such as SPI2, peripheral UART, Keyscan input/output, and ADC input). When not used in any special function modes, the GPIOs are initialized with input enabled by default at boot up. The 40 GPIOs (P0 through P39) are arranged in three ports as follows:
• P0 through P15 on port0
• P16 through P31 on port1
• P32 through P39 on port2
1. All GPIOs can be input and output disabled (high-Z), input enabled, or output enabled.
2. When the GPIO is input-enabled, an internal pull-up or an internal pull-down can also be optionally configured.
3. A GPIO that is output-enabled and driven high or low will remain driven in sleep and deep sleep.
4. All GPIOs are capable of being configured for edge (rising/falling/both) or level interrupts. An application level interrupt handler can be configured to handle the interrupt in the application thread context.
5. Interrupts can additionally be configured to wake the system from sleep and deep sleep.
6. All GPIOs can source or sink up to 2 mA. P26, P27, P28 and P29 can sink up to 16 mA.
Hi, having to connect the BCM20732S to our microcontroller, should I use the UART_TX and UART_RX signals or should I connect it to the pheriperhal UART of the module?
Could you please clarify me this point?
You will want to use the PUART, or peripheral UART as the HCI UART is dedicated to programming/debugging the device and cannot be attached to an external MCU.
You may want to take a look at the puart_control application within the SDK. There is also a sample application which demonstrates how to program the device over the PUART. Note that all initial programming of the part MUST occur over the HCI UART.
What are the voltage levels acceptable on peripheral UART TX/RX?
Specifically in input to P0,P1,P2 and P3?
Could my microcontroller at 3,3V connect directly or should I use a voltage translator?
Can you do a schematic review for me?
Acceptable voltage levels for the PAD IO are described here in the CYW20737S Bluetooth Low Energy SiP Module Technical Reference
There are many design files included on the website you can refer to as a design reference.
Contact your local Distributors for a more in depth review.
Sorry but there is a little confusion on what are the acceptable voltage levels on PUART pins: giving a look to the BCM20732 SoC datasheet, it reports that the PUART pins are on the 1,2V domain; on the other hand, on the BCM20732S module, there is no clear evidence that in the SiP block diagram, that voltage translators are included in the module.
Or is the "peripheral Interface block" in the SoC, the one that with its voltage translators in the 3,6V domain, allows directly communication with 3,3V input signals?
I believe this thread answers your question about the maximum voltage that can be applied to the PUART: BCM20732S Electrical Spec - Interfacing to Higher Voltages
1. What is the recommended maximum voltage that can be applied to any pin relative to VDDIO?
a. [JT] – 3.63V
I will ask jota_1939431 to confirm when he gets into the office this morning.
Max Voltage for BCM2073xS is 3.63V.
The more accurate answer is that the Maximum IO voltage cannot exceed 10% over VIO.