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Hi all,
Our target application requires digital filtering of 14 sensors, ie 14 IIR filters (4rth order BPF).
Can we implement more than 2 filters with digital filter block?
Also, can we implement a digital filter writing a new component for UDBs?
Thank you in advance,
John
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PSoC 5LP
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The digital filter block within a PSoC5 is a rather complex hardware part and there are only two channels availlable.
So two solutions come to my mind:
Software: Depending on your frequency requirements a software filter can use up a lot of CPU power, so a research how much a single channel calculation uses, will reveal how many filters could run in parallel.
UDB Hardware: There are 24 8-bit wide "Universal Digital Blocks" containing a few registers, an ALU that can perform some integer logic and arithmetic. So as long as a reduction of the filter into the "integer - world" lead to a solution.
A combination of both, hardware helping the software calculating, will probably the most powerful solution. Keep in mind,that the DMA system can be used to transfer data between components and UDBs.
Bob
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The digital filter block within a PSoC5 is a rather complex hardware part and there are only two channels availlable.
So two solutions come to my mind:
Software: Depending on your frequency requirements a software filter can use up a lot of CPU power, so a research how much a single channel calculation uses, will reveal how many filters could run in parallel.
UDB Hardware: There are 24 8-bit wide "Universal Digital Blocks" containing a few registers, an ALU that can perform some integer logic and arithmetic. So as long as a reduction of the filter into the "integer - world" lead to a solution.
A combination of both, hardware helping the software calculating, will probably the most powerful solution. Keep in mind,that the DMA system can be used to transfer data between components and UDBs.
Bob
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The target application needs very low power dissipation so the final choice depends on the current consumption each solution requires.
If I understand correctly, there is no way of implementing more than two digital filters within the DFBs.
I believe that hardware solution, implementing filters within UDBs, would consume less power than using the CPU so I will work into that direction.
If the complete filter(s) cannot fit in the available UDBs then I will try to follow combination of both software and hardware as you suggested.
One more question. Could I use VHDL, because I am familiar with that one or I should migrate to Verilog HDL?
Thank you very much for your reply.
John
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Clearing one misunderstanding: I was not talking about power dissipation, I was talking about MIPS, a software filter could use a lot of CPU cycles.
I did always use VeriLog for programming the UDBs, it is already integrated into Creator. There is some documentation (already installed with Creator): a Component Author Guide and a Warp Verilog Reference Guide, both to find under your PSoC Creator3.1\Component Development Kit\
Bob
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Thank you for your replies.
Sorry for this question bombing.
The DBFv1.30 component datasheet says "In addition, the system SW can ‘load sample or coefficient data in or out of the DFB data RAMs, reprogram for different filter operation in ‘block mode’, or both. This allows for multichannel processing or deeper filters than are supported in local memory." on Page 23.
I am confused. Does this mean that I could implement more than 2 filters with DFB component?
John
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I am afraid, no more than two (2) channels possible. Have a look at the DFB Assembler component which exposes two channels, too: To be really sure, create a MyCase and get answers from Cypress directly. Support & Community -> Technical Support -> Create a MyCase.
Can you tell us a bit more about the frequencies of your incoming signals?
Bob
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Thank you for your reply once more.
The sampling frequency of incoming signals is about 1KHz. Considering 14 signals, 14KHz could be sufficient.
It is not a high proccessing load. The task is to reduce power consumption of the chip.
John
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Running 14 (or 12) filters in software at 1ksps each leaves @60MHz ~4k cycles (5k). That could be doable using some optimizations.
Why do you need to reduce the power consumption?
Bob
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The sampling frequency of incoming signals is about 1KHz. Considering 14 signals, 14KHz could be sufficient.
You would need to oversample the input freq by ~ 10, in order to get desired
response. Use the filter wizard and experiment with a cascaded biquad to get the
LPF and examine sample rate effects.
You could consider using the DFB assembler to time share the DFB and possibly
get the thruput you are looking for. In my opinion I think the goals are aggressive,
only a test case will reveal if possible.
http://www.cypress.com/?rID=60720 DFB Assembler, MAC Topics
https://www.youtube.com/watch?v=2UC4gCohrk8 DFB Video Part I
https://www.youtube.com/watch?v=6tr_CNWIA8M DFB Video Part II
https://www.youtube.com/watch?v=nIa4X7gES3k DFB Video Part III
Regards, Dana.
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Thank you both for your reply and for your time sharing information.
The target application will be portable device and that is why we need to reduce power consumption.
Optimizations so far include integer operations instead of floating-point and the minimum scaling up to maintain accuracy.
I know that the goal is very ambitious. The oversampling suggestion will be taken into account... even if it almost killed me 🙂
I use Matlab for filters simulation and I will check the effects on various sampling frequencies. I will also study the DFB to create a test app.
John
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You could get in touch with filterwizard@cypress.com and ask for guidance.
Kendall Castor Perry.
Or file a CASE -
To create a technical or issue case at Cypress -
“Support”
“Technical Support”
“Create a Case”
You have to be registered on Cypress web site first.
Regards, Dana.
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As a favor to the forum post back the results you get from
Kendall or a CASE. I would certainly be interested.
Regards, Dana.
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Thanks again for your replies.
I will study better first and then I will create a case.
I will share Interesting conclusions.
John
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I am sure you already thought about this, but how long will one measurement be or does it have to be continous?
Do the 14 inputs have to be sampled simultaneously or can there be a (longer) time shift in between?
Where lastly go the 14 filtered values to?
Bob
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The specification is that input signals are read (almost) concurrently.
Filtered values are combined to each other and further (but not complex up to kow) processing takes place to produce a vector output that is transmitted wireless to a station.
John
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@jvourv
Read this article till the end:
It seems that your task can be accomplished (theoretically). Practically, as Bob mentioned above, you need to contact the author (K.Castor-Perry) for assistance, as no code examples are given.
odissey1
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Thanks for the interesting article.
I will study it in detail.
John
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Note, when you work with the DFB Filter Wizard, you may have to
move the corner freq to get the cutoff you want for a given attenuation
level. Thats just one more design input you can adjust at will.
Regards, Dana.
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Thank you for your notice.
I will take that into account.
John
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You are always welcome!
Dana.