SAR ADC 1mhz sample rate clock setting

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WaMa_286156
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  I am trying for 1,000,000 sps from the SAR, single channel.

   

  The GUI only lets me set 666,667 or 1,333,334 samples per second. Never 1 million.

   

  Does anyone know how to get 1msps from the ADC?

   

   thanks ahead of time!

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HeLi_263931
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Probably the clock you are using has the wrong frequency. Do you use an external or an internal one? The external one must be 18MHz, if you are using an internal one there must be one with is a multiple of that (e.g. MASTER_CLK)

   

(Maybe post your project here so we can have a look - 'File / Create Workspace bundle')

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WaMa_286156
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 OK.  That is probably the problem.  Will test.

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Bob_Marlowe
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You need an xtal stabilized clock, look at attached project.

   

 

   

Bob

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WaMa_286156
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  OK.  I understand now.  Thank you, Bob, for the example.

   

  Basically, the SAR ADC needs an external 18mhz clock.

   

  I'll start a thread on clocks, I have some questions there after looking at the data sheet.

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Bob_Marlowe
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No, you are wrong. The sar ADC does not need an external clock.

   

When you run the ADC at 1Msps you are so near at the limits of the hardware, that the 2.5% uncertainity of the IMO violates some setup times. So, what you need is a 24MHz xtal and 2 Cs (~10pF and 12pF). the IMO then can be set to 36MHz (derived from the 24MHz by the PLL) which is a mutliple of 18 and so will give you the desired frequency results. If you are satisfied with some lower sps, leave the xtal and set the IMO to 34MHz which will give you an ADC-clock of 17MHz resulting in 0.944Msps (17/18).

   

 

   

Bob

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WaMa_286156
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 Ah!  I understand better now.  I also did not explain very well what I meant.  Foot in mouth again.

   

.

   

What I should have said is that I need to set up the SAR for external clock in the schematic, and bring in an 18mhz clock into the SAR in order to get the divisor for 1msps.  Sorry about that.

   

.

   

I do have to pay attention to the clock domain due to the extreme nature of the operating environment the device will encounter.

   

.

   

Temperatures may be extreme.  We expect failures after a certain number of hours or temperature excursions.  During some of the excursions, AT cut crystals could have frequency excursions that go asymptotic.   The key is to allow operation as far out as possible.  If it dies, it dies.

   

.

   

I'm hoping to do some testing at around 700,000 sps.  That should be within the SAR setup time specs, even with the resonator inside the device.

   

.

   

Thanks, Bob.  You are  a very good source of information.

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WaMa_286156
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  An update to this thread.

   

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  The latest SP2 for PSoC Creator from Cypress changes the number of clocks required for the SAR to finish completion.  It now takes 16 clocks rather than 18 clocks. 

   

.

   

If you update your components in an older project, things will change......

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ETRO_SSN583
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WaMa_286156
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 That is interesting, I just noticed the XTAL clock source note.  That appears to mean that you can't use XTAL clock input at 16mhz into the ADC.

   

  Wonder how you would get 1mhz, then?  Curious.

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ETRO_SSN583
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I will post a CASE on this and get clarification.

   

 

   

Regards, Dana.

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Bob_Marlowe
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You usually do not feed the xtal directly into your ADC. You use a high precision clock to substitute the less precize IMO. My version 3.0 of the SAR still takes 18 cycles, so when I set the PLL frequency to 36MHz I can get 1Msps.

   

 

   

Bob

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ETRO_SSN583
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This was done with 3.1 SP2, internal clock -

   

 

   

   

 

   

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ETRO_SSN583
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Back from tech support -

   

 

   

    

   

          

   

With Vref as Bypassed or external and the Master clock being an integral

   

multiple (36 MHz, 54 MHz) of ADC clock (18 MHz), 1 MSPS sampling rate

   

with 12 bit resolution can be achieved.

   

 

   

Regards, Dana.

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WaMa_286156
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 As I  understand it, the CPU runs at twice the master clock frequency (48mhz for 24mhz master)

   

 Therefore, we are causing the CPU to run at 72mhz.  This is out of spec for all but the higher speed parts.

   

  Or, am I missing something?

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WaMa_286156
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 Evidently, the GUI has not kept up with the data sheet.

   

The data sheet specifically states that 16 clock cycles are used for a converstion.  The GUI still believes there are 18 clock cycles for a conversion.  According to the data sheet, it is wrong.

   

  Changing to 36mhz does not give you any way to get 16mhz, and the PLL can't synthesize 16mhz from any imo input that I have tried.  I also tried 15 mhz from the PLL and got another error.  I tried a 16mhz crystal and got an error.  I tried a 32mhz crystal, and it was outside the crystal oscillator's range.

   

  So, best I can tell, the SAR cannot do 1MSPS any more, if the data sheet is correct for the 3.0 update.

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ETRO_SSN583
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If you look at the clock tree I configed and the settings for the SAR that compiled.

   

 

   

Note the response I got from tech support was still thinking the 18 samples.

   

 

   

Regards, Dana.,

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WaMa_286156
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 Oh, yes, I understand what you are saying.

   

  The datasheet says it takes 16 clocks, and that is 16 mhz.  therefore 18mhz clock would cause it to convert beyond the 1mhz specification.

   

   So, is the data sheet wrong, or is the GUI and PSoC creator internals wrong?

   

  I vote for the GUI, because I suspect the GUI is lagging behind.   It always takes time for software to catch up with hardware.

   

  The hardware data sheet says that it will take 16mhz to convert at the maximum 1msps for that ADC, and the GUI is feeding it 18mhz, which will probably fail, or at the very least, give you bad readings.

   

   I have successfully compiled stuff on PSoC in the past that did not work.  This may indeed work, but I don't know for how long, or for how well.

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WaMa_286156
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   I was able to get a 32mhz PLL by running the IMO at 24mhz.  (any other frequency, the 32mhz is not exactly 32).

   

   With that, I was able to divide down to 16, and feed into the SAR.   

   

   Tracking the EOC with a frequency counter, this gives us slightly more than 1 MSPS, probably due to the IMO inaccuracy.

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HeLi_263931
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The 16 clock cycles are only for the "internal Vref" option. And the GUI reflects that properly. If you select "Internal Vref bypassed" its still 18 cycles. (And the data sheets says s explicitely)

   

But since using the internal Vref without bypassing is only usable for up to 100ksps, its not interesting for getting 1Msps. The GUI doesn't reflect this limitation, though, and the project also builds fine.

   

I just tested seting the SAR ADC to bypassed Vref, feeding it a 18MHz clock, and the project builds fine.

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WaMa_286156
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 Very good!  You are right!

   

  The note at the end of the document threw me off, stating categorically that there were 16 clocks per conversion.  I never differentiated between internal vref and internal vref  (with bypass).  That nailed me.

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HeLi_263931
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Yeah, the text in the changelog can be confusing. But the actual part where the configuration is explained is very specific that the 16 cycles only apply for that specific configuration.

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Anonymous
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I was trying to configure the SAR ADC to run at 10KHz, but the GUI does not allow me to do so. 

   

I am using PSOC Creator 3.3 & PSOC5LP device CY8C5866LTI-LP022, ADC reference in se to internal & no bypass. 

   

When I change the frequency to a lower frequency than 100000 the GUI pops an error saying that "Conversion rate for internal Vref must be less than 100000 SPS" . Any hints ?? 

   

My IMO Clock is set to 3MHz, PLL Clock, Master and Bus Clocks are set to 66MHz. 

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Bob_Marlowe
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Use a timer component to generate an clock running on your desired conversion frequency. Use the eoc connectes to an interrupt to fetch the data from the SAR.

   

 

   

Bob

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