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I don't understand the question. Could you please elaborate? For master mode, you can use pins from table 3 and for slave mode, you can use pins from table 4. Another (expanded) form of this information is in include/Drivers/spiffydriver.h, Spi2MasterGpioConfigType and Spi2SlaveGpioConfigType (enums for all valid master and slave pin assignments for the chip). Make sure that you don't violate the restrictions if you are also using peripheral uart and that the pins are available on the module/SoC.
The table 3 and table 4 is actually a matrix.
I want to know that if I want to select three pins for CLK, MISO and MOSI, whether they should be on same row?
In the Table 3 row 1, P3, P0 and P1 are assigned for spi master, can I use P25 to replace P1 as MISO because P25 and P1 are on same colume.
The pins you select for each function should all reside within the same horizontal row.
"In the Table 3 row 1, P3, P0 and P1 are assigned for spi master, can I use P25 to replace P1 as MISO because P25 and P1 are on same colume"
No, the pins have to exist in the same horizontal row, not vertical or horizontal.
spi_comm_master sample application in SDK uses P24 for CLK, P4 for MOSI, P25 for MISO.
P24 stays different horizontal row with others.
So I think P3(CLK), P0(MOSI) and P25(MISO) would work.
OK, I understand.
As per table 3 row 3, there are just two pins for spi clk and mosi, P24 and P27, but miso is disappear, it is not an integrity SPI port, is it meaningful?
1. Connect Slave device to SPI interface and FCO
* (Use P2 for CS, P24 for CLK, P4 for MOSI, P25 for MISO, and P14 for FCO)
I think they are not on the same row.