Delta sigma ADC low accuracy problem

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Anonymous
Not applicable

hi,

   

I'm kind of new in pSoc and one of my first projects is creating some kind of a probe in pSoc 5LP, using an ADC_delsig component

   

the problem is that the  output of the ADC is very far from the Vref input I'm inserting.

   

the design I have built is made of 3 components : an ADC_delsig , a LCD, and a Vref.

   

the Vref is the input of the ADC (the other one is the component Vssa), and the output of the ADC  is converted into uV and displayed in the LCD

   

if I'm inserting an input of 1.024V the output is around 1,022,000 uV  (0.2%)

   

and if I'm inserting an input of 0.256V the output is around 251,000 uv (2% error !!!!)

   

can somone explain me why the second output error is so big ?

   

 

   

thanks

   

Yossef

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Bob_Marlowe
Level 10
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Welcome to the forum, Yossef.

   

To reduce noise use reference: Bypassed and add a cap to GND at the selected pin.

   

The Buffer Mode can be set to Disabled.

   

Remember that you can set the parameters offset and gain to get a more precise result.

   

From datasheet of VRef component:

   

Note that the 1.024-V voltage reference calibration occurs for the buffered ADC_DelSig
reference. All of the other 1.024-V references (about 7 or 8 different ones) can be off by several
millivolts.

   

The 0.256V reference is derived from a 1.024V reference.

   

 

   

Bob

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HeLi_263931
Level 8
Level 8
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There is no specification how accurate the resistive divider for getting th 0.256V reference is.

   

But note that you specified "rail-to-rail" as input buffer mode - that means your input voltage range goes only down to 100mV. Maybe change that to "level shift" and try again.

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ETRO_SSN583
Level 9
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ETRO_SSN583
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These might be of use -

   

 

   

    

   

          

   

http://www.cypress.com/?rID=39677     AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations

   

http://www.cypress.com/?rID=40247     AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations

   

http://www.cypress.com/?rID=39974     AN58304 - PSoC® 3 and PSoC 5LP – Pin Selection for Analog Designs

   

http://www.cypress.com/?id=4&rID=49491     Power measurements for low power modes of PSoC 3/5 on CY8CKIT-001

   

 

   

 

   

Regards, Dana.

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Anonymous
Not applicable

 Hello,

   

I also encountered the same problem as in this thread, I noticed inaccurate voltage measurement when using a SAR or delta-sigma ADC. I used both Vref and a VDAC as to create voltage sources and measurement, and got inaccurate measurement with both ADCs.

   

I don't understand the answers to the question in the thread.

   

what are the steps that should be taken (as simple as possible), to get the ADC' specified accuracy? I expect an error that is smaller than 1 mv if possible, so I used 12 bit accuracy.

   

Do you need to add a connection from Vref to a capacitor and from the capacitor to the ground?

   

If so, what is the capacitance of the  capacitor that should be used? Is there an available capacitor in the board itself (050 Kit) to use or should I use an external capacitor and connect it via the pins and cables to the prototyping area?

   

Also, I saw that Dana gave links to documents that discuss the internal chip wiring. Is it necessary to deal with that for simple ADC conversion?

   

Thanks,

   

     Peli

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ETRO_SSN583
Level 9
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From the TRM -

   

 

   

   

 

   

Herer is Vref from -050 schematic -

   

 

   

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ETRO_SSN583
Level 9
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The point of the internal ref picture of PSOC was to

   

show where the reference is being supplied to on the

   

chip, informational purposes only.

   

 

   

What do your measurements look like, values, etc. ?

   

 

   

Consider posting your project so code can be looked at.

   

 

   

    

   

         

   

“File”                                                             Creator

   

“Create Workspace Bundle”

   

 

   

 

   

Lastly if you are at 12 bits, and setup for 5V then 1 LSB =~ 1.22 mV.

   

If you use your DSO in infinite persistence and look at power supply

   

rails you will see probably 100 - 200 mV of noise, that is ~ 100 LSBs.

   

So board layout critical and how you route and condition signals into

   

the chip. The following ap notes show just how difficult mixed signal

   

hi res A/D measurment can be, especially over temp.

   

 

   

www.dropbox.com/s/ruaf9booe17jk8n/PCB%20Layout.zip

   

 

   

Lastly if you are using VDAC to supply Vx to the A/D, its is only 8 bits.

   

So your measurment is off intrinsically by 16 LSBs to start with

   

at 12 bit measurements, and that does not include the error the VDAC

   

has.

   

 

   

The most importent thing to do in precision A/D processing, or signal chain,

   

is to do an end to end error analysis, all offsets, noise, current offsets, CMR,

   

PSRR, INL......otherwise you are just blowing smoke in a design as to what

   

you can guarentee for absolute accuracy.

   

 

   

Regards, Dana.

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