Welcome to the forum, Yossef.
To reduce noise use reference: Bypassed and add a cap to GND at the selected pin.
The Buffer Mode can be set to Disabled.
Remember that you can set the parameters offset and gain to get a more precise result.
From datasheet of VRef component:
Note that the 1.024-V voltage reference calibration occurs for the buffered ADC_DelSig
reference. All of the other 1.024-V references (about 7 or 8 different ones) can be off by several
The 0.256V reference is derived from a 1.024V reference.
There is no specification how accurate the resistive divider for getting th 0.256V reference is.
But note that you specified "rail-to-rail" as input buffer mode - that means your input voltage range goes only down to 100mV. Maybe change that to "level shift" and try again.
These might be of use -
http://www.cypress.com/?rID=39677 AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations
http://www.cypress.com/?rID=40247 AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations
http://www.cypress.com/?rID=39974 AN58304 - PSoC® 3 and PSoC 5LP – Pin Selection for Analog Designs
http://www.cypress.com/?id=4&rID=49491 Power measurements for low power modes of PSoC 3/5 on CY8CKIT-001
I also encountered the same problem as in this thread, I noticed inaccurate voltage measurement when using a SAR or delta-sigma ADC. I used both Vref and a VDAC as to create voltage sources and measurement, and got inaccurate measurement with both ADCs.
I don't understand the answers to the question in the thread.
what are the steps that should be taken (as simple as possible), to get the ADC' specified accuracy? I expect an error that is smaller than 1 mv if possible, so I used 12 bit accuracy.
Do you need to add a connection from Vref to a capacitor and from the capacitor to the ground?
If so, what is the capacitance of the capacitor that should be used? Is there an available capacitor in the board itself (050 Kit) to use or should I use an external capacitor and connect it via the pins and cables to the prototyping area?
Also, I saw that Dana gave links to documents that discuss the internal chip wiring. Is it necessary to deal with that for simple ADC conversion?
From the TRM -
Herer is Vref from -050 schematic -
The point of the internal ref picture of PSOC was to
show where the reference is being supplied to on the
chip, informational purposes only.
What do your measurements look like, values, etc. ?
Consider posting your project so code can be looked at.
“Create Workspace Bundle”
Lastly if you are at 12 bits, and setup for 5V then 1 LSB =~ 1.22 mV.
If you use your DSO in infinite persistence and look at power supply
rails you will see probably 100 - 200 mV of noise, that is ~ 100 LSBs.
So board layout critical and how you route and condition signals into
the chip. The following ap notes show just how difficult mixed signal
hi res A/D measurment can be, especially over temp.
Lastly if you are using VDAC to supply Vx to the A/D, its is only 8 bits.
So your measurment is off intrinsically by 16 LSBs to start with
at 12 bit measurements, and that does not include the error the VDAC
The most importent thing to do in precision A/D processing, or signal chain,
is to do an end to end error analysis, all offsets, noise, current offsets, CMR,
PSRR, INL......otherwise you are just blowing smoke in a design as to what
you can guarentee for absolute accuracy.