Peripherals / master clock influence at CPU clock

[Anonymous]

Hi

   

We are new to PSoC, and currently investigating it for a new project, where we need shift registers to clock data in and out.

   

We compiled the shiftreg example project, changing it to 32 bit wide, and setting master / bus clock to 66MHz.. STA reports setup violation and f max is 53MHz.. Lowering the master / bus clock to 48MHz removes the violation.

   

According to doc. bus / CPU clock must be equal or lover than master clock ( UDB clock ? ). It looks like the use of UDB's and perhaps other peripherals will put restrictions to the CPU speed ?

   

Is this really correct, or am i missing something

       

Thanks

   

Geert

[Bob_Marlowe]

Welcome in the forum, Geert!

   

Yes, there are some dependencies between SysClock and a derived clock which is generated by dividing SysClock or IMO. The components themselves have a maximum clock speed. Since you may have clocks with self-defined frequencies it will be easy to keep up with the given speed-limits stated in the component's datasheet which is 50MHz in your case. Getting a 50MHz clock implies that your original clock frequency must be a multiple of that value (50MHz) which is only the 50MHz itself. But running the shift register at a lower frequency as 24, 18 or 12 MHz could be maintained by selecting an appropiate value of the SysClk.

       

Bob

[Anonymous]

Rhanks Bob,

   

Yes but how do you lower shift reg speed to eg 12MHz, and still have CPU at eg 60MHz. ?

   

In the PSoC Creator shift register example project, IMO is set to 3 and PLL out is set to 60MHz, to get 60MHz CPU speed. How is the shift register speed set to 12MHz. ?

   

Geert

[Bob_Marlowe]

The shift register has an input clock. Connect that input to a clock component for which you can specify any clock value you need. When you cannot get it to work, consider posting your complete project here. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.



Bob
 

[Bob_Marlowe]

Configuration example project attached. Additionally you can right-click on the shift register component and select "find Example Project".

       

Bob

[ETRO_SSN583]

Something like this -

               

http://www.cypress.com/?rID=40990     AN60631 - PSoC® 3 and PSoC 5LP Clocking Resources

[Anonymous]

Thanks Bob,

   

I'II look at it

       

Geert

[Anonymous]

I found my problem.

   

It is actually the control Reg component used in the shift reg example which caused trouble. It was set to direct mode. It need to be set to Sync, and sync'ed to slower clock ( eg 12 MHz ).

   

Thanks everyone

       

Geert

[Bob_Marlowe]

Geert, you are always welcome!

       

Bob