So I dropped the clock frequency down and it seems to run as expected at 1MHz.
Maybe there is an issue with the propagation delays at higher frequencies?
Most of the basic components run up to 48MHz clock, so the issue will be caused by something different. Can you please post your complete project (with the AND-gate) with all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
You disabled the instruction cache?
Would be easier to use the enable input for the PWMs to start (and stop) counting instead of gating the clocks
You could use a two (2) output configuration which will be synchronus by design
It was a bit late yesterday night, so I will explain today my suggested changes:
Reset signal must be synchronus to clock
TC is one clock pulse
=> when tc is internally derived from Clk the rising edge of the reset signal may come too late and will not be seen.
In other words: When deriving the reset signal directly from Tc there might be some tough setup and hold times. Have a look at the diagrams in the PWM datasheet.
Problem could be solved by using a Pulse Converter component to get a reset pulse long enough.
From datasheet reset is synch -
This shows reset being used directly from Tc.
Hi Bob & Dana,
Thanks for such thorough help. I ended up dropping the gate and shifting the control reg to the reset line to get things moving.
I didn't want to use the dual output because this is an early stage in a more sophisticated system.
Regarding the instruction cache, I used an example project to get things moving and that must have been a remnant from the original program. Where did you see that and how can I re-enable it?
On the *.cydwr file shown in workspace explorer
The heap and stack size were reduced in 3.1, try restoring to 3.0 levels 4K and 16K respectively.
3.1 default settings are now 128 bytes and 2K.