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Dear developers ,
This may be very basic. How does one handle sudden level changes in the signal to be digitized by an ADC while it is currently in conversion mode. Does an ADC on the PSoC IC have any inbuilt sample and hold function in its input to maintain a constant input signal level during conversion or does it only have a garbage value when this kind of a situation occurs? please clarify.
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PSoC 5LP
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SAR -
DelSig -
The DelSig also has a clock related sampling time. See www.cypress.com/
As you stated yes you have constraints on the input stability necessary. You can make
a calculation on resolution requred vs sample time in the sampling period (clocks) in
order to determine what how much you need to band limit signal. Here is a settling
time calculator - designtools.analog.com/dt/settle/settle.html
There is a component Sample/Track and Hold that can be used to assist with this
problem.
Regards, Dana.
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Dear Dana,
Thanks for the reply. If I have understood it right the ADC component
DOES NOT HAVE A SAMPLE & HOLD facility
and it is the responsibility of the designer to make provisions for handling the fast variations
in the signal compared to the sampling rate either by using a separate sample and hold component or a low pass filter. If my understanding is wrong please correct me.
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Generally speaking that is correct.
If you look at the SAR a portion of the conversion time is constrained
by sampling, such that you could use that in your analysis and approach
to providing the band limited signal and/or S/H approach.
Regards, Dana.
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Dear Dana,
I have a situation where I cannot put a filter in the input since I want to digitize a signal in its pristine form. The problem is there is lot of step variation in the signal. For example if the current level of the signal is at say 500 mV and I am in the process of digitizing this value, there is a very great chance that this level would change to 600mV in a matter of nanoseconds that too during the mid of current digitization. the ADC conversion process started with the in put of 500 mV but before even the conversion ended the value has changed tp 600mV. Now assuming there are no more changes in the signal what would be the ADC value corresponding to after the current conversion?. will at all the ADC be able to settle at a binary value?
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Let me ask what you want the digital signal to "settle" to? By definition, an analog signal is constantly changing with time. Digitization simply chops the continuous time into little samples of delta t. So in audio, a low sampe rate results in poor sound quality while a high sample rate results in higher sound quality. So what did you expect to see -- 500 or 600 on your readout? You just took a sample at some delta t.
If your purpose is to look at pulses (such as a DMA 2-clock pulse signal to an interrupt) on an oscilloscope, use a pulse converter to increase the length of the pulse so that you can see it on the o'scope.
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Which A/D are you going to use ?
What you describe is a non band limited signal, so Nyquist is out the window.
Keep in mind the DelSig is inherently LP due to Sinc filter implementation. So
steps are bandlimited.
Is your interest in instantaneous values or average or RMS or peak or ?
Regards, Dana.