[BCM20732] SPIFFY2 Slave and Peripheral UART

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Anonymous
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Hi sirs,

If I want to keep both interface exist, can I arrange the pin assignment as follow?

SPIFFY2 -> CS(P02), SCLK(P03), MOSI(P00) and MISO(P05).

UART -> RXD(P4), TXD(P32)

I read the BCM920732_HW_Application_Note and have a question about the restrictions.

If a peripheral UART is also being used by the application, the SPIFFY2 signals and peripheral UART RX signal must be on the lower pad bank (P0 through P7) or on the upper pad bank (P24 through P39). Thus, SPIFFY1 or SPIFFY2, and peripheral UART RX, cannot be on two different pad banks.

What does it exactly means?

Best regards,

Fran

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1 Solution

You can use any row for the signals, but they have to be from the same group. So P32 and P33 for TXD and RXD is fine. The TXD columns are the same in both groups, so if you don't need HW flow control, you can choose TXD and RXD from either groups. But if you do need HW flow control, all four signals have to be from the same group.

GPIOs in black are available in the 32-pin package (and so with Chip-on-board designs). The ones in red are on the SoC, but are not brought out on the 32-pin package. The 2073XS modules follow the 32-pin package GPIO availability  very closely, but there are some differences. Please see the module datasheet, but the rules for PUART pin assignment still have to follow the two group tables.

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MichaelF_56
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Within the 920732HW-AN100-R AppNote, I do not see where RXD(P4) and TXD(P32) is listed as a valid combination for the Peripherhal UART.

RXD(P2) and TXD(P0) may be a better option.

For SPIFFY2 try SCLK(P03), MOSI(P04) and MISO(P01)

This would satisfy the requirement that the SPIFFY2 signals and peripheral UART RX signals are all on the lower pad bank (P0 through P7).

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Anonymous
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Hi, I'm a little confused about the document that describe the signal muxing..

For example, the Page15. How to understand this table?ScreenClip.png

Another example of Page16, The code example below the table use the RxD with P33 and TxD with P32.

ScreenClip.png

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If the Pxx Logical Pin Mapping is noted in black, then it's available for the intended function.

If listed in Red, it's not.

arvinds j.t

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Anonymous
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Does it means the RXD(P4), TXD(P32), such kind of UART combination is workable?

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I wasn't able to find a horizontal line under the peripherhal UART where UART -> RXD(P4), TXD(P32) are both black.

Based on my understanding of the table, this indicates tha tthe combination is not valid.

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Anonymous
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Hi,

The reason why I paste the captured photo is because the sample code in this document use P33 and P32.

They are not in the same horizontal line, and that's the reason why I want to ask how to read the table.

ScreenClip.png

ScreenClip.png

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I will see if I can get one of the developers to respond.

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You can use any row for the signals, but they have to be from the same group. So P32 and P33 for TXD and RXD is fine. The TXD columns are the same in both groups, so if you don't need HW flow control, you can choose TXD and RXD from either groups. But if you do need HW flow control, all four signals have to be from the same group.

GPIOs in black are available in the 32-pin package (and so with Chip-on-board designs). The ones in red are on the SoC, but are not brought out on the 32-pin package. The 2073XS modules follow the 32-pin package GPIO availability  very closely, but there are some differences. Please see the module datasheet, but the rules for PUART pin assignment still have to follow the two group tables.

Anonymous
Not applicable

Hi, I got the EVK and start testing on it. In the SDK1.1 uart_firmware_upgrade sample mention if we use the serial flash, we have to use P24 and P25 typically. So, what's the SPI pins we can assign?

screenshot.png

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Note that this comment may only apply to an SOC discussion since the following pins on the module are shared with SPIFFY1 and currently being used by the internal I2C:

  • Pin 21 SCL I/O, PU Clock signal for an external I2C device, shared with SPI_1 SCLK
  • Pin 22 SDA I/O, PU Data signal for an external I2C device, shared with SPI_1 MOSI

Based on my understanding, serial flash cannot be used with the current module since the I2C/SPIFFY1 is already occupied by the EEPROM.

arvinds j.t

Anonymous
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If I replace the EERPOM by the SPI flash, I can use the Pin21(SPI_1 SCLK) and Pin22(SPI_1 MOSI).

Then, which pin I can use for SPI_1 CS and SPI_1 MISO?

Besides, the SPI1 can only be master right? Is it possible to make it as slave?

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P32 is MISO and P33 is CS. Please check the datasheet for the physical pin numbers on the module/package.

> Is it possible to make it [SPI1] as slave?

No. SPI1 is master only. Use SPI2 for slave mode.