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Hi,
I'm writing my own component and I was wondering if there is a power verilog operator? I don't see any documentation on it and I keep getting a syntax error whenever I try to use the ** in my code.
Thanks,
Scarlson
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In Cypress help, documentation, warp verilog guide I see no operator listed -
But in Cadence manual this -
Regards, Dana.
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In Cypress help, documentation, warp verilog guide I see no operator listed -
But in Cadence manual this -
Regards, Dana.
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so I'm guessing thats a no for verilog then? the cadence manual is referring to VHDL, while the other is referring to verilog.
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Seems like its hard to completely disassociate Warp VHDL and Warp Verilog, from the Cypress manual
introduction -
Point being Verilog is RTL based like VHDL, and seems like its an extension
to VHDL at some level ? Not an expert here, you are talking to a dunce.
Regards, Dana.
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