Routing 32 KHz ILO output to pin in PSOC4-BLE in deep sleep mode.

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Anonymous
Not applicable
0 Likes
8 Replies
ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

The LFCLK can be directly routed to a pin -

   

 

   

   

 

   

Regards, Dana.

0 Likes
Anonymous
Not applicable

Thanks. I am able to get LFCLK as an output to GPIO in Active mode.

   

 

   

But I am trying to assign 32 khz in deep sleep mode to one of the GPIO pins.

   

 

   

Thanks.

0 Likes
ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

Looks like the pin is frozen -

   

 

   

   

 

   

Regards, Dana.

0 Likes
Anonymous
Not applicable

 GPIO output states cannot be changed during Deep-Sleep.

0 Likes
lock attach
Attachments are accessible only for community members.
Anonymous
Not applicable

 Thanks For the info.

   

 

   

I am able to get 8KHz clock in deep sleep mode using LCD drive in deep sleep mode.

   

Is it possible to get 32 KHz in deep sleep mode?

   

I have attached the project for reference. 

   

 

   

Thanks.

0 Likes
Anonymous
Not applicable

 DSI connection is lost during Deep Sleep. That is why you do not see the clock when directly routed to a Pin during Deep Sleep. The max frequency using Segment LCD method is 8 KHz.

0 Likes
lock attach
Attachments are accessible only for community members.
Anonymous
Not applicable

Finally I am able to get 32KHz WCO output in deep sleep mode.

   

          

   

We need to enable LFCLK as WCO in .cydwr. Now using the High Speed I/O Matrix (HSIOM), we can route this clock to Pin. In this project, we are routing to P1[0]. Please note that this is only available for three Pins P1[0], P2[3] and P3[7].

   

The example project uses P1[0]. 

   

If you want to route it to P2[3], then configure P2[3] as an output pin in Creator and write:

   

 *(uint32*)CYREG_HSIOM_PORT_SEL2 |= 0x0000F000 ;

   

 Similarly, for P3[7], you need to write:

   

 *(uint32*)CYREG_HSIOM_PORT_SEL3 |= 0xF0000000 ;

   

 after configuring P3[7] in Creator as an output Pin.

0 Likes
ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

I would be a great assist to all if you filed a case and asked Cypress

   

to update TRM, clocking section, and any applicable ap notes, like

   

the low power ap notes and the coming clock ap note. Just paste in

   

your findings when you file your CASE.

   

 

   

    

   

         

   

To create a technical or issue case at Cypress -

   

 

   

www.cypress.com

   

“Support”

   

“Technical Support”

   

“Create a Case”

   

 

   

You have to be registered on Cypress web site first.

   

 

   

Regards, Dana.

0 Likes