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Hi,
I have a problem with noise. Can check the image that the blue is a sign almost no noise (https://www.dropbox.com/s/ijswxkjcemlxt0m/High%20frequency%20noise%21%21.jpg?dl=0)
The purple is a signal just outside Two Opamp Topology (equal to figure 3 of this article http://www.cypress.com/?docID=41827) with gain = 2.
As you can see the signal have some strange peaks.
They know how I can fix this?
Best regards.
Solved! Go to Solution.
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PSoC 3
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Can you post your complete project, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file. Do not forget the scope settings and the pictures.
Bob
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Can you post your complete project, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file. Do not forget the scope settings and the pictures.
Bob
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This ap note is in major error. You cannot use 2 PGAs to create an IA as their
G matching accuracy is so poor it virtually destroys all CM which is the reason
for using an IA in the first place.
http://www.cypress.com/?app=forum&id=2492&rID=82151 IA CMR Analysis
www.dropbox.com/s/plck7e95v7pw33c/CMR%20Analysis%20IA.pdf
The only way to build an IA in PSOC is to use a thin film precision R network to set up
G in the IA front end, using PSOC OpAmps. Even then the Aol matching of the OpAmps
will limit your CM performance.
Regards, Dana.
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Looks like R1 and R2 are swapped in value. But you still have
a basic problem, you cannot use a PGA in an IA because its G
accuracy is so poor part to part. If you want CM rejection either you
use precision Rs external (thin film array) coupled with onboard
OpAmps or an external IA, the latter emminently preferred.
What CM rejection spec do you want ?
In the ref material I posted is extensive analysis of 2 and 3 OpAmp
IA CM performance. And requirments on the Rs.
Regards, Dana.
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Here is an analysis due to Aol differences onchip between OpAmps -
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Several considerations -
1) Input signals to any pn in PSOC must meet Vdda >= Vinpout >= Vssa
2) OpAmps and PGAs need to be biased up to meet common moide ranges
In your case, G = 2, say you have a 1V sine into part, then AC couple it in.
To set bias Ideally you want the 1 V sine to swing around 2.5 V on output as
bias (5 V Vdda). So the VDAC would be 1.25 V. x G of 2 = 2.5 output bias point.
Regards, Dana.
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Another way of biasing -
The sharp spikes make me think you have some coupling going on into
PGA input from ajacent pins with digital signals on them ?
Regards, Dana.
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Thanks. 😉
problem solved.
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What was the error / cause you found ?
Regards, Dana.
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the error is in PGA. i need to use more power...
it's strange error...but now it's ok.
thanks
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When PGA is used on lower power its GBW and slew rate drop. In some
control loops this would allow greater transients to occur, ie. its not reacting
to change fast enough.
But the nosie youw ere experiencing does not "normally" occur because of the
above, so I am stumped as well.
Regards, Dana.