Anonymous
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Jul 22, 2015
06:30 AM
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Jul 22, 2015
06:30 AM
Hello,
I'm currently designing a FPGA (Altera Cyclone V) core connected to the GPIF2 interface.
Unfortunately I couldn't constraint my design that it is running at maximum frequency of 100MHz.
Especially the CTL hold time of 0 ns is generating failing hold time violations.
Could somebody successfully connection an Altera FPGA to the FX3 GPIF2 interface and
running that interface @ 100MHz ?
Any comment is welcome.
Thanks,
Achim
1 Reply
Anonymous
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Aug 02, 2015
12:00 PM
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Aug 02, 2015
12:00 PM
Hi,
The altera Cyclone 3 FPGA has been interfaced with FX3 DVK at 100 MHz and the project (both FX3 firmware and FPGA project) are available here
Regards,
-Madhu Sudhan