Timing running FX3 GPIF2 @ 100MHz

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Anonymous
Not applicable

Hello,

   

I'm currently designing a FPGA (Altera Cyclone V) core connected to the GPIF2 interface.

   

Unfortunately I couldn't constraint my design that it is running at maximum frequency of 100MHz.

   

Especially the CTL hold time of 0 ns is generating failing hold time violations.

   

 

   

Could somebody successfully connection an Altera FPGA to the FX3 GPIF2 interface and

   

running that interface @ 100MHz ?

   

 

   

Any comment is welcome.

   

 

   

Thanks,

   

Achim

0 Likes
1 Reply
Anonymous
Not applicable

Hi,

   

The altera Cyclone 3 FPGA has been interfaced with FX3 DVK at 100 MHz and the project (both FX3 firmware and FPGA project) are available here

   

Regards,

   

-Madhu Sudhan

0 Likes