even though i don't have any layout constraints (that i know of), the fitter complains:
Error: plm.M0005: Fixed location constraints could not be satisfied during macrocell to LAB packing. See report file for more information. (App=cydsfit)
ERROR: Fixed location constraints could not be satisfied during macrocell->PLD packing.
is this a common problem? my circuit is pretty trivial.
the complete error message is included here:
<CYPRESSTAG name="PLD Packing">
Error: plm.M0005: Fixed location constraints could not be satisfied during macrocell to LAB packing. See report file for more information. (App=cydsfit)
ERROR: Fixed location constraints could not be satisfied during macrocell->PLD packing.
Constraint failure occurred when trying to place the following macrocell
into the PLD at location [UDB=(3,0)][LB=1][MC=1]:
MacroCell: Name=COMM_STATE_0, Mode=(T-Register) @ [UDB=(3,0)][LB=1][MC=1]
Total # of inputs : 0
Total # of product terms : 0
List of special equations:
Clock = (COMM_CLK_IN)
Reset = (Net_1015)
Clock Enable: True
Main Equation : 0 pterms
!(
0
);
Output = COMM_STATE_0 (fanout=11)
Properties :
{
}
Destination PLD had the following contents:
LAB@[UDB=(3,0)][LB=1] #macrocells=1, #inputs=0, #pterms=0
{
[McSlotId=0]: (empty)
[McSlotId=1]: (empty)
[McSlotId=2]: (empty)
[McSlotId=3]: MacroCell: Name=COMMAND_MODE, Mode=(D-Register) @ [UDB=(3,0)][LB=1][MC=3]
Total # of inputs : 0
Total # of product terms : 0
List of special equations:
Preset = (Net_619_3)
Clock Enable: True
Main Equation : 0 pterms
(
0
);
Output = COMMAND_MODE (fanout=11)
Properties :
{
}
}
