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Forget marketing. Is UART supported on this ?
When interrupt is set internal RX interrupts don't trigger, except UART_INTR_RX_OVERFLOW
When switched to external neither of interrupts trigger.
My code:
EXT_UART_Interrupt_StartEx(myinterrupt_func);
UART_Start();
UART_SetRxInterruptMode(UART_INTR_RX_NOT_EMPTY|UART_INTR_RX_OVERFLOW);
UART_SetTxInterruptMode(UART_INTR_TX_NOT_FULL|UART_INTR_TX_UART_DONE);
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And ofcourse:
CY_ISR_PROTO(myinterrupt_func);
CY_ISR(myinterrupt_func){
}
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Did you enable global interrupts. Without seeing project hard to judge
what is going on.
“File” Creator
“Create Workspace Bundle”
Regards, Dana.
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I've succeeded. RX interrupts are triggered when all intr (RX) are on.
However during all interrupts (around 😎 FIFO is empty , so no data read (and no error). I love it
UART_RX_FIFO_STATUS_REG is 0 all the time
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Do You know any UART example working with ProcBLE and Tx and Rx enabled?
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Do You know any TRM for this chip?
How could it be, that RX_INTR_NOT_EMPTY is triggered, but _RX_FIFO_STATUS_REG is 0? My imagination is failing
Status reg inform about data available (first 3 bits)
At the same time fifo ctrl reg is 7
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As Dana already suggested:
Can you please post your complete project, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
Bob
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What does it mean if on FIFO reg(0x40240340) there is a value 0xFF, but Cypress API return 0?
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How can you be sure that you are referring to the right register (0x...) after a build? Maybe you've reset the bits already by reading them.
Post your project, we'll see.
Bob
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As always marketing is far ahead of reality.
in my case FIFO has 0xFF. then fifo is translated into uint32. SO we have 0xFFFFFFFF. Then we get error value and or with FIFO
result. In my case (ff OR 0x40) has ff which means error is ff.
This is the first BUG i've found here
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How could it be, that NOT_EMPTY event is triggered, but where FIFO read we have event 0x40 ( trying to read empty FIFO)?
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To Bob:
What I see is related to any UART example, so neither example can work. This is why CYpress published example which read FIFO without interrupts. My UART case is real life scenario, and polling byte by byte is not possible
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This is a cypress code where BUG is:
rxData = Sim900_RX_FIFO_RD_REG;
>>>rxData is 0xFFFFFFFF. How 8-bit FIFO data can become 32bit value is another story to investigate
/* Enables interrupt to receive more bytes.
* The RX_NOT_EMPTY interrupt is cleared by the interrupt routine
* in case the byte was received and read by code above.
*/
#if (Sim900_CHECK_RX_SW_BUFFER)
{
Sim900_EnableInt();
}
#endif
}
/* Get and clear RX error mask */
tmpStatus = (Sim900_GetRxInterruptSource() & Sim900_INTR_RX_ERR);
Sim900_ClearRxInterruptSource(Sim900_INTR_RX_ERR);
/* Puts together data and error status:
* MP mode and accept address: 9th bit is set to notify mark.
*/
rxData |= ((uint32) (tmpStatus << 8u));
>>>rxData is 0xFFFFFFFF again masking error
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Without your complete project (or at least a project that shows the error) anything could be guessing only.
What are the component's buffer size? which component do you use and which version? Any other settings that could affect your receiving?
# of bits, baud, clock settings.......
Bob
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I agree. Painful problem isolation. Create the test case is time consuming but I have to find time.
Meantime I've found out that UART_DONE (for TX line) interrupt loops forever blocking chip functionality.
ClearTxInterruptSource(UART_INTR_TX_UART_DONE); doesn't work
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I disagree, that any example project help isolate the problem. I think it's related to external party sending data, and PSOC internal guts.
I'm running different example with the same external hardware and the problem is the same.
Every character received I get 0xFFFFFFFF on FIFO hardware afterwards .buffer which is not example project dependent, and should never happen.
So once again character received correctly then 0xFFFFF... then another character
This is probably the reason , that data sent into PSOC with 11520b/s are partially skipped. Therefore garbage is returned.
The transmission is checked in parallel with another UART gear RX pin, and there is no communication problem with external hardware.
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My interrupt routing which might matter is :
if (UART0_GetRxInterruptSource() & UART0_INTR_RX_NOT_EMPTY) {
UART0_ClearRxInterruptSource(UART0_INTR_RX_NOT_EMPTY); // clear interrupt
d = UART0_UartGetByte();
if ((d & 0xFFFFFF00) == 0) {
c = d;
if ( (c != ' ')&&(c != '\n') ) {
goto _process;
}
} else {
c = d >> 10;
_process:
i = headRx + 1;
if ( i >= RX_BUFFER_SIZE) i = 0;
if (i != tailRx)
{
rxPool[headRx] = c;
headRx = i;
}
}
}
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You still did not post your complete project (or a reduced but working one) to have us look at all of your settings. With your code snippets not all questions can be answered, but you can take for sure that the UART component is running flawlessly (I use it every day for debugging purposes) so something in your project will be wrong, give us a chance to find that. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
Bob
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I doubt it, but is it possible that your Cypress UART issue is related to the module going into deep sleep mode by
CyBle_EnterLPM(CYBLE_BLESS_DEEPSLEEP)?