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Hello,
I am planning to use a CY8C56xx with a WaveDAC8 as current source/sink on a variable external load. This load includes the possibilities of becoming open or too large to power (ie Rload * WaveDAC8_Amplitude > VCC- Voverhead ) and I would like to know what behavior to expect from the WaveDAC8 module during these time?
Does the WaveDAC8 include protection against these modes, and if so, what are the ranges of this protection?
Are there indicators of these faults occurring? I haven't seen any in the component documentation, but I want to verify this.
Any advice, or links to appropriate documentation, is appreciated!
ngohara
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PSoC 5LP
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I am planning to use a CY8C56xx with a WaveDAC8 as current source/sink on a
variable external load. This load includes the possibilities of becoming open or too
large to power (ie Rload * WaveDAC8_Amplitude > VCC- Voverhead ) and I
would like to know what behavior to expect from the WaveDAC8 module during
these time?
The current generator will come out of compliance once you exceed its min operating V.
For the case where external load is a power generator -
If you exceed the rails you will start drawing a lot of current due to pin protection diodes.
Too much current and you will trigger the parasitic SCR which in turn will draw very large\
currents, and or blow the internal power bond wires to chip with permanent damage. The
latchup current rating is 140 mA, enough to generate significant die hot spots and melt
silicon possibly.
For case where external load is a real resistance, current generator simply out of
compliance, regulation.
Does the WaveDAC8 include protection against these modes, and if so, what are
the ranges of this protection?
NO, for external power generator case, otherwise none needed, generator simply not
functioning properly.
Are there indicators of these faults occurring? I haven't seen any in the component\
documentation, but I want to verify this.
None that you can get your hands on given scr mechanism can trigger in uS range. Diodes
turn on even faster. You could use a comparator that generates an ISR or the A/D and
measure Vcurrentsource/sink, but thats not fast enough in the power generator case to
protect if its capable of power source/sink > rails.
Regards, Dana.
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Thank you for the advice.
Just to clarify, by "power generator" you mean the case where WaveDAC8_current * RLoad is higher than Vsupply, right?
There should be no external power connected to this part of my system.
Secondly, in the case of exceeding the rails, is there a module or an internal routing scheme I can implement to prevent the drastic hardware failure you describe? My system Will vary to extremely high Rloads at times, so preventing hardware damage is important in this case. It is understood that we will not be able to actually supply current in this case, or the open load case.
Thirdly, do you know what the WaveDAC8's response is in the open loop case?
Thank you again for the advice, and any other advice or links to documentation is appreciated!
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Just to clarify, by "power generator" you mean the case where WaveDAC8_current * RLoad is higher than Vsupply, right?
By this I mean an Rload in series with another V generator. Such that a condition could
occur where that generator started supplying current into the pin/Idac output. If you have
just a R load, nothing else, all that will happen at high values of Rload or opens is that
the current source will come out of compliance/regulation. No damage in this case or
special considerations needed. Other than your own circuit functionality considerations.
Secondly, in the case of exceeding the rails, is there a module or an internal routing scheme I can implement
to prevent the drastic hardware failure you describe?
Limit pin currents when any input is outside rails + ~ 1 diode drop with a series R
between pin and generator of the transient. For example if your signal path to pin
had a lot of L in it, opr laod dump capacitors.....
My system Will vary to extremely high Rloads at times, so preventing hardware damage is important in this case.
In your case no issue as stated above in first point.
Thirdly, do you know what the WaveDAC8's response is in the open loop case?
You would see the output saturate to ~ 1 volt below Vdd rail. Test it, simple to do in Creator.
Regards, Dana.
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Here is a Wavedac feeding a 2.7 K R, range set to 2.040 mA. The R value will
force the Idac out of regulation as you can see in attached pic.
You can see the Idac in the WaveDAC craps out at ~ 3.6 V, note Vdda was 4.5V in this
case so that was a complience of ~ .9 V, not taking into account all other errors. ~ spec
of the PSOC 5LP
Regards, Dana.
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Thank you for all the help, that was what I needed determine!
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Glad to be of assistance.
Regards, Dana.